Method to reduce bit line capacitance in cub drams

Details Method to reduce bit line capacitance in cub drams Method to reduce bit line capacitance in cub drams

2001-06-18

2002-10-29

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C257S300000

Reexamination Certificate

active

06472266

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to fabricate Capacitors Under the Bit line (CUB) of DRAM devices. The bit line contacts are provided with a surrounding air gap, reducing the parasitic capacitance between the bit line and the capacitor that is created under the bit line.
(2) Description of the Prior Art
Developments in the semiconductor industry have over the years been aimed at creating higher performance devices at competitive or lower prices. These developments have resulted in extreme miniaturization of semiconductor devices, which has been made possible by numerous and mutually supporting advances in semiconductor processes and by advances in the materials that are used for the creation of semiconductor devices, this in combination with new and sophisticated device designs. While most semiconductor devices are aimed at processing digital data, Dynamic Random Access Storage (DRAM) devices incorporate data retention or storage capabilities in the design of the semiconductor device. The creation of capacitive components, which are the basis for the data storage capabilities of DRAM devices, must emphasize that these capacitive components are created on a relatively small surface area of a semiconductor substrate while using methods and procedures that are well known in the art of creating semiconductor devices.
It is well known that capacitors can be created between layers of polysilicon, poly to polycide or metal or between layers of metal. Capacitors can be either of a planar design, for reasons of process simplicity, or can be three-dimensional, resulting in a smaller footprint as commonly used in DRAM devices.
Dynamic Random Access Memory (DRAM) devices typically consist of arrays of memory cells that perform two basic functions, that is the field effect transistor that serves as a charge transfer transistor and a capacitor. The field effect transistor (a source region, a drain region and a gate electrode) serves the function of providing access to the capacitor, the capacitor serves the function of data retention or storage. Binary data is stored as an electrical charge on the capacitor in the individual DRAM memory cells. Contacts to the surrounding circuits are provided for the DRAM memory cell. DRAM memory is so named because DRAM cells can retain information only for a limited period of time before they must be read and refreshed at periodic intervals. In a typical DRAM construction, one side of the transistor is connected to one side of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connect points that form the bit and word lines. The other side of the capacitor is connected to a reference voltage.
In creating storage capacity in semiconductor memory devices, it is essential that storage node capacitor cell plates are large enough so that an adequate voltage can be retained on the capacitor plates. This even in the presence of parasitic capacitances and circuit noise that may be occur in the circuit during circuit operation. With the continuing increase in circuit density, this latter requirement becomes even more of a challenge in maintaining required storage capabilities. Future generations of dynamic memory storage devices are expected to continue to evolve along the path of further miniaturization and will therefore continue to pose a challenge in creating capacitive storage capabilities at decreasing device dimensions. As the DRAM technology continuous to be scaled down, the height of the storage capacitor needs to be increased further in order to maintain large enough capacitive storage capability for each memory cell. This poses a challenge of reducing parasitic capacitive effects that, with the increase in the height of the storage capacitor, tend to have an increasingly negative effect on the DRAM cell storage capability. The invention addresses this concern and provides a method whereby the effect of parasitic capacitance is reduced for capacitors of increased height by introducing an air-gap as part of the structure.
U.S. Pat. No. 6,168,989B1 (Chiang et al.) shows a crown COB capacitor.
U.S. Pat. No. 6,110,775 (Fujii et al.), U.S. Pat. No. 6,165,839 (Lee et al.), U.S. Pat. No. 6,074,908 (Huang) disclose related capacitor patents.
U.S. Pat. No. 6,140,200 (Eldridge) shows voids and capacitor processes.
SUMMARY OF THE INVENTION
A principle objective of the invention is to create a capacitor-under-bit-line (CUB) whereby parasitic capacitance between the bit line contact and the CUB is significantly reduced.
Another objective of the invention is to create a capacitor-under-bit-line (CUB) that results in a significant reduction of the signal-to-noise ratio during the sensing operation of the DRAM cell.
Yet another objective of the invention is to provide a method of creating CUB DRAM devices that have been provided with an oxide ring surrounding polysilicon plugs.
In accordance with the objectives of the invention a new method is provided for the creation of the bit line contact plug. CUB capacitors typically are located adjacent to the bit line contact plug, a parasitic capacitance therefore exists between the CUB and the contact plug. The interface between the CUB and the bit line contact plug typically consists of a dielectric. By creating an air gap that partially replaces the dielectric between the CUB and the bit line contact plug, the dielectric constant of the interface between the bit line and the CUB is reduced, thereby reducing the parasitic coupling between the bit line contact plug and the CUB. This enables the creation of CUB capacitors of increased height, making the CUB and the therewith created DRAM devices better suited for the era of sub-micron device dimensions.


REFERENCES:
patent: 6074908 (2000-06-01), Huang
patent: 6110775 (2000-08-01), Fujii et al.
patent: 6140200 (2000-10-01), Eldridge
patent: 6165839 (2000-12-01), Lee et al.
patent: 6168989 (2001-01-01), Chiang et al.
patent: 6229174 (2001-05-01), Parekh
patent: 6300667 (2001-10-01), Miyamoto
patent: 2001/0044181 (2001-11-01), Nakamura
patent: 2001/0045658 (2001-11-01), Deboer et al.

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