Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2001-01-19
2004-08-17
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S787000, C438S788000, C438S790000
Reexamination Certificate
active
06777347
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication processes and more specifically to processes of fabricating porous silicon oxide for low dielectric constant films utilized in semiconductor fabrication.
BACKGROUND OF THE INVENTION
Current methods to form low density, porous silicon oxide for low dielectric constant films are relatively complex whereby an organic group containing a silica precursor is deposited in a chemical vapor deposition (CVD) reactor. Afterwards, the organic group is removed by heating in an oxidizing gas environment to create a porous oxide.
The disadvantages of such a process include the need for multiple process steps, and the relatively high process cost. Furthermore, heating in a furnace to remove the organic group has the potential risks of device shift and metal line deformation due to the high furnace temperature process.
For example, U.S. Pat. No. 6,054,206 to Mountsier describes a CVD process for producing low-density, porous oxides in a vacuum environment. An organic-group-containing silica precursor is deposited on a semiconductor substrate in a CVD reactor. The organic groups are then removed by heating in a furnace in an oxidizing environment or by exposure to an oxidizing plasma, thereby creating a low density silica film.
U.S. Pat. No. 5,824,375 to Gupta describes a chamber coating (seasoning) process before a CVD oxide deposition. A plasma clean process is used to remove sorbable contaminants such as fluorine. The chamber is then seasoned to block or retard remaining contaminants.
U.S. Pat. No. 5,635,102 to Mehta describes a thermal oxide deposition process and etch methods.
U.S. Pat. No. 5,840,631 to Kubo et al. describes a CVD silicon oxide formation method directly on a surface of a semiconductor substrate. A compound gas having a catalysis for promoting formation of silicon oxide is added in an atmosphere using a main component gas consisting of ozone, water vapor, and one of alkoxysilane and organosiloxane as a source gas to form a silicon oxide.
U.S. Pat. Nos. 6,114,216 and 6,099,647, both to Yich et al., describe system, method, and apparatus for high temperature (at least about 500 to 800° C.) processing of semiconductor wafers.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method to form a porous, low density silicon oxide film within a single process chamber.
Another object of the present invention is to provide a method to form a porous, low density oxide film using a relatively low temperature process to avoid any impact on semiconductor device performance.
Yet another object of the present invention is to provide a method to form a porous, low density oxide film having a formation temperature compatible with back-end multilevel metal interconnection without causing metal deformation and/or melting.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a CVD chamber having inner walls and a wafer chuck/heater is provided. At least a portion of the CVD chamber inner walls is pre-coated with a layer of first PECVD silicon oxide film having a first thermal CVD oxide deposition rate thereupon. A semiconductor wafer is placed on the wafer chuck/heater within pre-coated CVD chamber. The semiconductor wafer including an upper second PECVD silicon oxide film having a second thermal CVD oxide deposition rate thereupon that is less than the first thermal CVD oxide deposition rate upon the first PECVD silicon oxide film coating the CVD chamber inner walls. A porous silicon oxide film is deposited upon the upper second PECVD silicon oxide film overlying the semiconductor wafer. The porous silicon film being different from the first PECVD silicon oxide film coating the CVD chamber inner walls.
REFERENCES:
patent: 5635102 (1997-06-01), Mehta
patent: 5824375 (1998-10-01), Gupta
patent: 5840631 (1998-11-01), Kubo et al.
patent: 5904566 (1999-05-01), Tao et al.
patent: 6054206 (2000-04-01), Mountsier
patent: 6054735 (2000-04-01), Ngo
patent: 6099647 (2000-08-01), Yieh et al.
patent: 6114216 (2000-09-01), Yieh et al.
patent: 6149987 (2000-11-01), Perng et al.
patent: 6194304 (2001-02-01), Morozumi et al.
patent: 6348415 (2002-02-01), Lee et al.
Ni Chyi-Tsong
Su Eric
Ackerman Stephen B.
Brewster William M.
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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