Method to increase the area of a stacked capacitor structure by

Details Method to increase the area of a stacked capacitor structure by Method to increase the area of a stacked capacitor structure by

1997-04-09

1998-08-18

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438964, H01L 218242

Patent

active

057958068

ABSTRACT:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a grated top surface topography for a polysilicon storage node electrode. The grated top surface topography is obtained by using a composite spot structure, of silicon oxide on small diameter, HSG polysilicon spots, as a mask for an anisotropic dry etch procedure, used to define lower features in an underlying polysilicon layer. The raised features of the grated top surface topography of the polysilicon storage node electrode, is comprised of the masking, small diameter, HSG polysilicon spots, on regions of the unetched polysilicon layer.

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patent: 5492848 (1996-02-01), Lur et al.
patent: 5521408 (1996-05-01), Rha et al.

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