Method to increase capacitance of a DRAM cell

Details Method to increase capacitance of a DRAM cell Method to increase capacitance of a DRAM cell

1998-05-22

1998-11-17

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438398, H01L 218242

Patent

active

058375821

ABSTRACT:
A process for forming an HSG silicon layer, to be used as a component of, as well as to increase the surface area of, a polysilicon storage node electrode, has been developed. The process features initially depositing a polysilicon composite, comprised of underlying, undoped polysilicon layer, and an overlying, doped polysilicon silicon layer, resulting in an initial degree of surface roughness. The process continues with the deposition of an amorphous silicon layer, and an in situ anneal procedure, resulting in the conversion of the amorphous silicon layer, to a HSG silicon layer. The storage node electrode is then formed, comprised of the roughened HSG silicon layer, overlying the polysilicon composite.

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