Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-19
2001-10-02
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S981000
Reexamination Certificate
active
06297099
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of integrated circuit devices and specifically to fabrication of floating gates that may be used in FLASH memory devices.
BACKGROUND OF THE INVENTION
The interpoly/oxide thickness of the poly tip of a floating gate is limited by the thickness of the sidewall oxide of the floating gate. A thinner interpoly oxide would increase erasing speed, but would also decrease the programming speed due to the decreased source/floating gate coupling ratio. A thicker interpoly oxide would decrease erasing speed and endurance.
The interpoly oxide thickness of the poly tip is also limited by the word line oxide of the source/drain area. A thinner interpoly oxide would again increase erasing speed but would reduce the oxide breakdown strength of the word line when erasing with high voltage force.
For example, U.S. Pat. Nos. 5,879,992, 5,950,087, and 5,970,371 all to Hsieh et al describe split gate processes with interpoly oxide layers.
U.S. Pat. No. 5,453,388 to Chen et al. describes a split gate EEPROM with an interpoly oxide layer.
U.S. Pat. No. 5,330,938 to Camerlenghi describes another split gate process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention is to provide an method to fabricate a floating gate/word line having increased erasing speed while maintaining the programming speed and the oxide breakdown strength of the word line when erasing with high voltage force.
Another object of the present invention is to provide a method to fabricate an interpoly/oxide at the poly tip of a floating gate with a thickness thinner than the interpoly/oxide at the sidewalls of the floating gate and thinner than the word line oxide.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.
REFERENCES:
patent: 5330938 (1994-07-01), Camerlenghi
patent: 5453388 (1995-09-01), Chen et al.
patent: 5879992 (1999-03-01), Hsieh et al.
patent: 5950087 (1999-09-01), Hsieh et al.
patent: 5970371 (1999-10-01), Hsich et al.
patent: 6001690 (1999-12-01), Chien et al.
patent: 6046086 (2000-04-01), Lin et al.
patent: 6090668 (2000-06-01), Lin et al.
Chang Chung-Li
Chu Wen-Ting
Hsieh Chia-Ta
Jung Lin Chrong
Kuo Di-Son
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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