Method to form shallow trench isolations with rounded...

Details Method to form shallow trench isolations with rounded... Method to form shallow trench isolations with rounded...

1999-09-27

2001-05-08

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S445000

Reexamination Certificate

active

06228727

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the fabrication of shallow trench isolations in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolations (STI) are a method used to provide insulated isolations between active device areas in the semiconductor substrate. The use of STI has increased in recent years in the art of integrated circuit manufacturing. Formerly, local oxidation of silicon (LOCOS) was the dominant technique used to provide substrate isolation. STI has a much flatter topology than LOCOS. In addition, STI structures do not create perimeter bird's beak structures that can cause reliability and electrical performance problems.
Referring to
FIG. 1
, a cross-section of a partially completed prior art shallow trench isolation is shown. A semiconductor substrate
10
of silicon is shown. A pad oxide layer
14
is grown overlying the semiconductor substrate
10
. A silicon nitride layer
18
is deposited overlying the pad oxide layer
14
. The silicon nitride layer
18
and the pad oxide layer
14
are patterned to form a hard mask. The openings in the hard mask are created to expose the semiconductor substrate
10
where the trenches are planned.
Referring to
FIG. 2
, trenches are etched into the semiconductor substrate
10
.
Referring to
FIG. 3
, an oxide trench liner layer
20
is grown overlying the semiconductor substrate
10
. This oxide trench liner layer
20
serves several purposes. First, it reduces stress in the semiconductor substrate
10
induced by the etch. Second, it provides some minimal rounding of the trench corners. Third, the oxide trench liner layer
20
provides some minimal protection against oxide recess, as will be seen in FIG.
5
. After the oxide trench liner layer
20
is grown, a trench fill layer
22
is deposited overlying the silicon nitride layer
18
and filling the trenches.
Referring to
FIG. 4
, the trench fill layer
22
is first polished down to the top surface of the silicon nitride layer
18
. Next, the silicon nitride layer
18
is etched away.
Referring now to
FIG. 5
, the trench fill layer
22
is again polished down. Once the trench fill layer
22
and pad oxide layer
14
are polished down to the surface of the semiconductor substrate
10
, the shallow trench isolation device is completed.
We note two potential problems with the prior art shallow trench isolation structure completed in FIG.
5
. First, the relatively sharp corners
30
of the STI structure can cause electrical parametric problems in MOS devices fabricated adjacent to the structure. For example, a subthreshold “V
t
-kink” can be seen in MOS transistors adjacent to a STI that has relatively sharp corners. Second, the final polish down of the trench fill layer
22
can cause a recession of the oxide
34
at the corners of the STI. This problem results in high junction leakage, especially if the device formed is salicided.
Several prior art approaches disclose methods to form trenches in the substrate in the fabrication of integrated circuits. U.S. Pat. No. 5,801,083 to Yu et al discloses a process to form shallow trench isolation with rounded corners. Polymer spacers are formed to cause a widening of the silicon nitride mask above the shallow trenches. After the polymer spacers are removed, a thermal oxide is grown to line the trenches. This approach has the disadvantages of possible carbon contamination due to the polymer and the difficulty of controlling the thickness of the polymer sidewalls. U.S. Pat. No. 5,866,435 to Park teaches a method to form shallow trenches where a first mask is formed exposing the substrate where trenches are planned. A second masking layer, of polysilicon or amorphous silicon, is deposited overlying the first mask and the exposed substrate. The second masking layer is etched anisotropically down. When exposed, the substrate is simultaneously etched down with the second masking layer. When the second mask layer is etched away, the shallow trench is completed. U.S. Pat. No. 4,857,477 to Kanamori discloses a process to fabricate a trench for a trench capacitor. An oxide mask overlying the substrate is etched to form openings for trenches. A second oxide layer is deposited and formed into oxide spacers on the sidewalls of the openings. The trenches are etched down into the substrate. The spacers are removed. The trenches are dry etched to round the edges. An insulator film is formed lining the trenches. Finally, conductive electrodes are formed inside the trenches. U.S. Pat. No. 4,707,218 to Giammarco et al teaches a process to make mask openings smaller than practical by photolithography. A photoresist layer is patterned. Sidewall spacers are formed to reduce the dimensions of the mask openings. U.S. Pat. No. 5,674,775 to Ho et al discloses a process to form trenches with rounded corners. Silicon nitride overlying pad oxide is patterned to form openings for the trenches. A polysilicon, or amorphous silicon layer, is deposited. The polysilicon layer is etched down anisotropically. The trench is etched into the substrate simultaneously with the polysilicon layer. U.S. Pat. No. 4,495,025 to Haskell teaches a process that uses sidewall spacers to create trenches of different depths in a silicon substrate.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating shallow trench isolations in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate shallow trench isolations with reduced oxide recession at the edges of the structures through use of sidewall spacers on the trench mask.
Another further object of the present invention is to provide a method to fabricate shallow trench isolations with rounded trench corners through use of sidewall spacers on the trench mask and sputter etching the shallow trench.
Another further object of the present invention is to provide a method to fabricate shallow trench isolations with rounded trench corners through use of sidewall spacers on the trench mask and hydrogen annealing the shallow trench.
In accordance with the objects of this invention, a new method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and the oxide trench lining layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.


REFERENCES:
patent: 4495025 (1985-01-01), Haskell
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4857477 (1989-08-01), Kanamori
patent: 5674775 (1997-10-01), Ho et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5801083 (1998-09-01), Yu et al.
patent: 5866435 (1999-02-01), Park
patent: 6020230 (2000-02-01), Wu
patent: 6074932 (2000-06-01), Wu
patent: 6080628 (2000-06-01), Cherng

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