Method to fabricate isolation by combining locos and shallow tre

Details Method to fabricate isolation by combining locos and shallow tre Method to fabricate isolation by combining locos and shallow tre

1998-11-02

2000-05-09

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438229, 438230, 438424, 438425, 438443, H01L 218238, H01L 2176

Patent

active

060603488

ABSTRACT:
A method for forming planarized isolation by combining LOCOS and STI isolation processes is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride layer and pad oxide layer are etched through where they are not covered by a mask to provide openings where the surface of the semiconductor substrate is exposed wherein there is at least one wide opening and one narrow opening. A second nitride layer is deposited over the substrate and etched back to leave spacers on the sidewalls of the openings wherein the narrow opening is filled by the spacers. The exposed semiconductor substrate within the wide opening is oxidized wherein a field oxide region is formed within the wide opening. A portion of the first nitride layer and spacers is etched away whereby the semiconductor substrate within the narrow opening is exposed. A trench is etched into the semiconductor substrate where it is exposed within the narrow opening. An oxide layer is deposited overlying the first nitride layer and field oxide region and filling the trench wherein the oxide layer filling the trench forms a shallow trench isolation region. The oxide layer is polished away with a polish stop at the first nitride layer. The first nitride layer, the spacers, and the pad oxide layer are removed, completing formation of both a field oxide region and a shallow trench isolation region in the fabrication of an integrated circuit device.

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