Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-12-12
2002-01-22
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S748000, C438S280000
Reexamination Certificate
active
06340628
ABSTRACT:
BACKGROUND
1. Field of Invention
The present invention relates to semiconductor processing, and in particular, to deposition of dielectric films.
2. Related Art
Integrated circuits fabricated on semiconductor substrates for very large scale integration typically require multiple levels of metal layers to electrically interconnect the discrete layers of semiconductor devices on the semiconductor chips. The different levels of metal layers are separated by various insulating or dielectric layers (also known as interlevel dielectric (ILD) layers), which have etched via holes to connect devices or active regions from one layer of metal to the next. The individual metal and ILD layers can be deposited by conventional chemical vapor deposition (CVD) techniques, such as high density plasma (HDP) CVD, plasma enhanced CVD (PECVD), or low pressure CVD. Typical dielectric materials for the ILD layer include silicon oxides, silicon nitrides, and silicon oxynitrides.
Current CVD processes typically utilize nitrous oxide (N
2
O) or O
2
as an oxidizing gas and N
2
as a balance or carrier gas in forming an ILD layer. Suitable precursor gases for such layers include multiple siloxanes, such as, but not limited to, tetramethyldisiloxane (TMDSO), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane (OMCTS). Other suitable precursor gases include alkylsilanes, such as 3MS, 4MS, and PTMS.
When N
2
O as an oxidizing gas or N
2
as a balance gas is used, unwanted nitrogen can build into the deposited films or layers, resulting in amines (NH
2
groups) formed on the surface of the film or layer. These amines cause photoresist “footing” when exposing the photoresist with deep ultraviolet (DUV) light, as discussed in more detail below.
As semiconductor technology advances, circuit elements and dimensions on wafers or silicon substrates are becoming increasingly more dense. Consequently, the interconnections between various circuit elements and dielectric layers also need to be reduced. Interconnections and other patterns are formed by etching specific portions of the metal and/or dielectric layer to electrically disconnect or connect active regions.
Typically, a photoresist layer of photo-reactive polymeric material is deposited over the layer to be patterned or etched. Light such as visible, ultraviolet (UV), or deep UV (DUV) light is directed through a mask onto the photoresist layer to expose the photoresist and transfer the mask pattern thereon. However, as feature sizes continue to decrease, the shorter wavelength light radiation is used to expose the resist. Whereas “I-line” radiation having a wavelength of 365 nm has been the standard, DUV radiation having a wavelength of 248 nm or less is now being used more frequently.
The exposure of photoresists that are used with deep UV radiation generally creates an acidic reaction in the photoresist. The resulting acidic compounds then react with the developer to create a mask. Since the amines are basic, they tend to neutralize the acids generated by the exposure of the photoresist and thereby inhibit the development of the photoresist. For example, some incident DUV light may be reflected from the underlying layer and scattered back into the photoresist, and contaminants from the underlying layer can migrate into the photoresist. As a result, when the photoresist is developed, the side walls are non-uniform (non-vertical), also known as photoresist “footing”. Consequently, the pattern in the photoresist that is subsequently transferred to the underlying layer is not the desired pattern, but will have errors resulting from the photoresist footing. This is especially critical with dense patterns and smaller feature sizes.
Accordingly, it is desirable to deposit a dielectric film without the problems discussed above that are associated with conventional techniques.
SUMMARY
In the present invention, a dielectric layer or film is deposited with a chemical vapor deposition process using a CO
2
-containing gas with a multiple siloxane or alkylsilane. The CO
2
-containing gas can include O
2
or a C
x
H
(2x+1)
OH compound, where 1≦x≦5. The resulting dielectric film or layer shows no photoresist “footing” caused by amines. Furthermore, the deposited layer has a low dielectric constant (e.g., k<3.0) and high adhesion and hardness properties.
The siloxane or alkylsilane flow is between 0.5 and 10 ml/min., and the CO
2
flow is between 500 and 5000 sccm. The deposition pressure is between 0.2 and 10 Torr, the deposition temperature between 25 and 425° C., the high frequency RF power between 150 and 2000 W. and the low frequency RF power between 0 and 500 W.
In one embodiment, the flow rate of O
2
is between 25 and 500 sccm, and in another embodiment, the flow rate of C
x
H
(2x+1)
OH is between 50 and 500 sccm. Both embodiments produce films with dielectric constants less than or equal to 2.8, hardness of 0.5 to 1.0 GPa, and adhesion of 2 to 6 kpsi.
The present invention will be more fully understood when taken in light of the following detailed description.
REFERENCES:
patent: 4002512 (1977-01-01), Lim
patent: 4902307 (1990-02-01), Gavalas et al.
patent: 5246734 (1993-09-01), Varaprath et al.
patent: 5447613 (1995-09-01), Ouellet
patent: 5457073 (1995-10-01), Ouellet
patent: 5543945 (1996-08-01), Kimura et al.
patent: 5789024 (1998-08-01), Levy et al.
patent: 5858065 (1999-01-01), Li et al.
patent: 6074698 (2000-06-01), Sakuria et al.
patent: 6245690 (2001-06-01), Yau et al.
Laxman Ravi Kumar
Nie Bunsen
Schulberg Michelle T.
Shu Jen
Van Cleemput Patrick A.
Chen Tom
Lebentritt Michael
Novellus Systems Inc.
Skjerven Morrill & MacPherson LLP
LandOfFree
Method to deposit SiOCH films with dielectric constant below... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to deposit SiOCH films with dielectric constant below..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to deposit SiOCH films with dielectric constant below... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2820612