Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-07-11
2006-07-11
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S107000, C438S113000, C438S633000, C438S926000, C257S629000
Reexamination Certificate
active
07074710
ABSTRACT:
A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.
REFERENCES:
patent: 4899195 (1990-02-01), Gotoh
patent: 5310626 (1994-05-01), Fernandes et al.
patent: 6268090 (2001-07-01), Matsubara et al.
patent: 6614507 (2003-09-01), Young et al.
patent: 6707535 (2004-03-01), Sato et al.
patent: 6812550 (2004-11-01), En et al.
patent: 6867842 (2005-03-01), Arao
patent: 2001/0033975 (2001-10-01), Chung et al.
patent: 2001/0049179 (2001-12-01), Mori
patent: 2002/0019091 (2002-02-01), Kim
patent: 2004/0253810 (2004-12-01), Wang et al.
patent: 2005/0110065 (2005-05-01), Uchiyama et al.
Ambercrombie David
Whitefield Bruce
Jr. Carl Whitehead
LSI Logic Corporation
Rodgers Colleen E.
Whitesell Eric J.
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