Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-13
2003-05-06
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S304000, C438S305000, C438S306000, C438S307000, C438S308000
Reexamination Certificate
active
06559017
ABSTRACT:
FIELD OF THE INVENTION
The present disclosure relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present disclosure relates to a method of using amorphous carbon as spacer material in a disposable spacer process.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). ICs often include flash memory cells.
Generally, a transistor is covered by a high temperature oxide and an interlevel dielectric to insulate it from subsequently formed metal layers. An aperture or hole is etched through the interlevel dielectric and the high temperature oxide. The hole is filled with a conductive material to provide connections to the transistor, to conductors, or other circuit structures. For example, a contact can extend from the bit line through the interlevel dielectric to the drain of the transistor. In another example, a contact or conductive via can extend through the interlevel dielectric to connect to the gate stack.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), CMOS fabrication processes must scale the dimensions of the transistors. That is, there must be proportional operational characteristics of structural elements in the ultra-small dimensions of a sophisticated transistor.
One problem associated with CMOS scaling involves short channel effects. In U.S. Pat. Nos. 5,985,726 and 6,271,095, both assigned to the assignee of the present disclosure, the formation of ultra-shallow source/drain regions to overcome short channel effects is discussed. Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions with less than 30 nanometer (nm) junction depth. Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channeling effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
U.S. Pat. Nos. 5,985,726 and 6,271,095 discuss the use of sacrificial or disposable spacers to surmount problems related to ultra-shallow source/drain extensions and pocket regions. In such processes, annealing processes for the pocket regions and the ultra-shallow extensions can be separated from annealing processing for the deep source and drain regions.
Conventional disposable spacer processes use nitride or oxide spacer materials that can have additional integration concerns. For example, use of nitride or oxide sacrificial spacers can require development of specialized selective etch chemistries and can cause active silicon gouging during spacer removal. Further, conventional disposable spacer processes have utilized conventional photoresist masking process which cannot achieve the resolutions of amorphous carbon processes.
Thus, there is a need to avoid concerns presented by nitride or oxide disposable spacers. Further, there is a need to use amorphous carbon in a disposable spacer process. Even further, there is a need to avoid special spacer etch chemistry and active silicon gouging by using amorphous carbon spacers.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of using amorphous carbon as spacer material in a disposable spacer process. The method can include forming amorphous carbon spacers at lateral side walls of a gate structure over a substrate, implanting dopants in the substrate to form source and drain regions, ashing away the amorphous carbon spacers to provide an aperture, and implanting dopants through the aperture to form shallow structures in the substrate.
Another exemplary embodiment relates to a method of disposable spacer utilization to avoid spacer etch chemistry and active silicon gouging. The method can include patterning a gate over a substrate, forming amorphous carbon spacers adjacent lateral side walls of the gate, forming source and drain regions in the substrate at locations not covered by the amorphous carbon spacer and the gate, removing the amorphous carbon spacers, and forming extension regions in the substrate at locations not covered by the gate.
Another exemplary embodiment relates to a method of forming ultra-shallow junctions using amorphous carbon spacers. The method can include providing amorphous carbon spacers adjacent sides of a gate located over a substrate, implanting source and drain implants to form source and drain regions in the substrate, ashing away the amorphous carbon spacers, activating dopants in the gate, and implant halo and extension implants.
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Brown David E.
Fisher Philip A.
Huang Richard J.
Nguyen Richard C.
Tabery Cyrus E.
Advanced Micro Devices , Inc.
Berry Rene′ R.
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