Method of surface treatment of semiconductor substrates

Details Method of surface treatment of semiconductor substrates Method of surface treatment of semiconductor substrates

1997-08-01

2001-07-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000

Reexamination Certificate

active

06261962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods of treatment for semiconductor substrates and in particular, but not exclusively, to methods of depositing a sidewall passivation layer on etched features and methods of etching such features including the passivation method.
2. Description of the Background Art
It is known to etch anisotropically trenches or recesses in silicon using methods which combine etching and deposition. The intention is to generate an anisotropic etch, whilst protecting the sidewalls of the trench or recess formed by laying down a passivation layer.
Such methods are for example shown in U.S. Pat. No. 4,579,623, EP-A-0497023, EP-A-0200951, WO-A-94114187 and U.S. Pat. No. 4,985,114. These all describe either using a mixture of deposition and etching gases or alternate etching and deposition steps. The general perception is that mixing the gases is less effective because the two processes tend to be self cancelling and indeed the prejudice is towards completely alternate steps.
Other approaches are described in EP-A-0383570, U.S. Pat. No. 4,943,344 and U.S. Pat. No. 4,992,136. All of these seek to maintain the substrate at a low temperature and at first, somewhat unusually, use bursts of high energy ions during etching to remove unwanted deposits from the sidewalls.
The continuous trend in semiconductor manufacture is for features of ever increasing aspect ratio, whence the sidewall profile and the surface roughness on the sidewalls, becomes more significant the smaller the width of the feature. Current proposals tend to produce a characteristically notched sidewall with poor CD control, reentrant sidewall profile as well as rough sidewalls and/or bases to the formations and depending on the process being run. The manifestation of these various problems depends on the application and the respective processing requirements; silicon exposed area (unmasked substrate area), etch depth, aspect ratio, sidewall profile, substrate topography.
SUMMARY OF THE INVENTION
The method of this invention, in at least some embodiments, addresses or reduces the problems described above.
One aspect the invention consists of a method of depositing a sidewall passivation layer on an etched feature in a semiconductor substrate, comprising placing the substrate in vacuum chamber, striking a plasma and introducing a hydrocarbon deposition gas to deposit a carbon or hydrocarbon layer.
This is in contrast to previous proposals which have deposited layers of the form CF
x
.
In a preferred arrangement the deposition gas includes H
2
, for example H
2
may be introduced with the deposition gas and the method includes determining the percentage of hydrocarbon gas in H
2
at which at least two of the following occurs:
(a) the etch rate begins to rise from a generally steady state
(b) the etch rate peaks
(c) the etch rate falls to zero
and subsequently performing the method of claim
1
with a hydrocarbon gas/H
2
mix which lies between a pair of (a), (b) or (c). In another preferred arrangement the deposition gas includes O,N or F elements and the deposited layer may be self biased in one arrangement to a relatively low voltage (to allow the ions to become accelerated to energies of several eV(≦20 eV)). In this case a mix percentage between (b) and (c) may be used. In another arrangement the ion energies are as high as several hundred eV in which case a mix percentage between (a) and (b) may be used.
The invention further consists of a method of etching a feature in a semiconductor substrate including alternatively etching and depositing a passivation layer wherein the deposition step is as defined above.
The prior art teaches the benefit of totally segregated etch and deposition steps. Alternatives to this, which address some of the aforementioned limitations are presented. The etching and deposition steps may overlap and etching and deposition gases may be mixed.
The method may include pumping out the chamber between etching akd deposition and/or between deposition and etching, in which case the pump out may continue until
Ppa
Ppa
+
Ppb
<
x
wherein Ppa is the partial pressure of the gas (A) used in the preceding step,
Ppb is the partial pressure of the gas (B) to be used in the subsequent step,
and
x is the percentage at which the process rate of the process associated with gas (A) drops off from an essentially steady state.
Depending on the precise process requirements and problems encountered with the prior art, the gases may be continuously or abruptly variable and indeed one or more of the following parameters: the gas flows rates, chamber pressure, plasma power, substrate bias and etching/deposition rate may vary periodically with the time for example as a sinusoidal, square or sawtooth wave form or a combination of these. For example the deposition and etching gases may be supplied so that their flow rates are sinusoidal and out of phase. The amplitude of any of these parameters may be variable within cycles and as between cycles. Benefits of the various approaches are given with typical processing conditions for a number of exemplary applications. In the particular case of CD (critical dimension) loss, initial ‘notch’ reduction is essential. When the silicon exposed area is relatively low (≦20%) and the corresponding etch rate is high, one solution that is preferred is that the deposition rate is enhanced and/or the etch is reduced during at least the first cycle and in appropriate circumstances in the first few cycles for example in the second to fourth cycles.
Other advantageous features of the method are that the etch and/or deposition steps may have periods of less than 7.5 seconds or even 5 seconds to reduce surface roughness; the etch gas may be CF
x
and may include one or more high atomic mass halides to reduce spontaneous etch; and the chamber pressure may be reduced and/or the flow rate increased during deposition particularly for shallow high aspect ratio etching where it may be accompanied by increased self bias.
The substrate may rest freely on a support in the chamber when back cooling would be an issue. Alternatively the substrate may be clamped and its temperature may be controlled, to lie, for example, in the range from −100° C. to 100° C. The temperature of the chamber can also advantageously be controlled to the same temperature range as the wafer to reduce condensation on the chamber or its furniture.
The substrate may be GaAs and in this case the etch gas may particularly preferably be one or a combination of Cl
2
, BCl
3
, SiCl
4
, SiCl
2
H
2
, CH
x
Cl
y
, C
x
Cl
y
, or CH
x
with or without H or an inert gas. Cl
2
is particularly preferred. The deposition gas may be one or a combination of CH
x
, CH
x
Cl
y
or C
x
Cl
y
with or without H, or an inert gas. CH
4
or CH
2
Cl
2
are particularly preferred.
Although the invention has been defined above it is to be understood that it includes any inventive combination of the features set out above or in the following description.


REFERENCES:
patent: 4533430 (1985-08-01), Bower
patent: 4599135 (1986-07-01), Tsunekawa et al.
patent: 4635090 (1987-01-01), Tamaki et al.
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4784720 (1988-11-01), Douglas
patent: 4795529 (1989-01-01), Kawasaki et al.
patent: 4832788 (1989-05-01), Nemiroff
patent: 4855017 (1989-08-01), Douglas
patent: 4985114 (1991-01-01), Okudaira et al.
patent: 5068202 (1991-11-01), Crotti et al.
patent: 5074955 (1991-12-01), Henry et al.
patent: 5079178 (1992-01-01), Chouan et al.
patent: 5368685 (1994-11-01), Kumihashi et al.
patent: 5474650 (1995-12-01), Kumihashi et al.
patent: 5478437 (1995-12-01), Hashemi et al.
patent: 5501893 (1996-03-01), Laermer et al.
patent: 5605600 (1997-02-01), Muller et al.
patent: 6051503 (2000-04-01), Bhardwaj et al.
patent: 0 160 220 A1 (1985-11-01), None
patent: 0 246 514 A2 (1987-11-01), None
patent: 0 350 997 A2 (1990-01-01), None
patent: 0 363 982 A2 (1990-04-01), None
patent: 0 383 570 A2 (1990-08-01), None
patent: 0 482 519 (1991-10-01), None
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