Method of structuring a semiconductor chip

Details Method of structuring a semiconductor chip Method of structuring a semiconductor chip

1992-01-30

1993-09-07

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156647, 156657, 1566591, 1566611, 156662, H01L 21306, B44C 122

Patent

active

052425339

ABSTRACT:
Processes are proposed for structuring monocrystalline semiconductor substrates provided with a basic doping, in particular silicon substrates with a (100) or (110) crystal orientation. In this process, at least one main surface of the semiconductor substrate is passivated by means of a structured masking layer, and in an etching step etching into the semiconductor substrate is done anisotropically through openings in the masking layer. It is proposed that as the masking layer (12), a structured, preferably monocrystalline, layer of the basic material of the semiconductor substrate be used, which is doped such that a pn junction is produced between the masking layer (12) and the semiconductor substrate (10), the junction being polarized in the depletion direction and serving as an etch stop. It is also proposed that the semiconductor substrate (10) be formed of a substrate (11) and at least one layer (13), applied thereon, with buried zones (16), with pn junctions being produced between the zones (16) and the substrate (11). Zones (16) that are electrically insulated from one another and the semiconductor substrate (10) are electrically bonded, so that the pn junctions are polarized in the depletion direction and serve as an etch stop for deep etching.

REFERENCES:
patent: 4672354 (1987-06-01), Kurtz et al.
patent: 4783237 (1988-11-01), Aine et al.
patent: 4966649 (1990-10-01), Harada et al.
patent: 5129983 (1992-07-01), Greiff
Anton Heuberger, Micromechanik, 1989, pp. 90-121 & 146-151, published by Springer Verlag, Berlin-Heidelberg--N.Y.--Paris--Tokyo.

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