Method of self-align cell edge implant to reduce leakage current

Details Method of self-align cell edge implant to reduce leakage current Method of self-align cell edge implant to reduce leakage current

1997-12-04

1999-10-26

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438266, 438451, H01L 218247

Patent

active

059727535

ABSTRACT:
A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.

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patent: 5888873 (1999-03-01), Krivokapic
S.Wolf, "Silicon Processing for the VLSI Era" vol. 2, Lattice Press, Sunset Beach, CA, 1990, p 632-4.

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