Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-06-07
1997-05-20
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438598, 438587, 438128, H01L 2170
Patent
active
056311834
ABSTRACT:
A semiconductor memory device with a memory array of cells formed as a matrix has bit lines, and word lines driven by word line drivers, where each of the word line drivers simultaneously selects and drives at least two word lines in order to minimize line resistances of the word lines, thereby minimizing a delay time and improving a speed of sensing a cell data. Accordingly a number of the word line drivers is at least one-half a number of the word lines.
REFERENCES:
patent: 4883980 (1989-11-01), Morimoto et al.
patent: 4906872 (1990-03-01), Tanaka
patent: 4926378 (1990-05-01), Uchida
patent: 4958092 (1990-09-01), Tanaka
patent: 5053993 (1991-10-01), Miura
patent: 5075890 (1991-12-01), Itoh
patent: 5097440 (1992-03-01), Konishi et al.
patent: 5097441 (1992-03-01), Cho et al.
patent: 5148401 (1992-09-01), Sekino et al.
patent: 5172335 (1992-12-01), Sasaki et al.
patent: 5457064 (1995-10-01), Lee
patent: 5460990 (1995-10-01), Bergemont
patent: 5496754 (1996-03-01), Bergemont et al.
patent: 5512504 (1996-04-01), Wolstenholme et al.
Kim Hyeun-Su
Lee Dong-Jae
Bushnell Esq. Robert E.
Nguyen Tuan H.
Samsung Electronics Co,. Ltd.
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