Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2000-06-12
2001-08-28
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S594000, C438S787000, C438S289000
Reexamination Certificate
active
06281140
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to reduce the roughness of a gate insulator layer, which had previously been subjected to a threshold voltage ion implantation procedure.
(2) Description of Prior Art
The desired threshold voltage, for both N channel, (NMOS), as well as P channel, (PMOS), metal oxide semiconductor devices, are usually accomplished via ion implantation procedures, performed through a gate insulator layer into the channel region of the complimentary metal oxide semiconductor, (CMOS), device. These implantation procedures, usually performed through a silicon oxide gate insulator layer, using boron or BF
2
ions, for both the NMOS and PMOS devices, can however result in an increase in the roughness of the surface of a silicon oxide gate insulator layer. The increase in surface roughness of the gate insulator layer negatively influences the coatablity of overlying photoresist layers, used to define subsequent device features.
This invention will teach a novel procedure used to restore the topography, or surface roughness of a silicon oxide gate insulator layer, which had been subjected to a boron type, threshold adjust, ion implantation procedure. Prior art, such as Gdula et al, in U.S. Pat. No. 3,925,107, describe a post-oxidation, anneal process which reduces the fixed charge, and fast states, in silicon dioxide, gate layers as thin as 100 Angstroms. However that prior art does address the novel process, now presented, allowing reductions in the surface roughness of the thin silicon oxide gate insulator layers, after the surface roughness of the gate insulator layer was increased as a result of being subjected to a threshold adjust implantation procedure.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate NMOS and CMOS devices, featuring a threshold adjust procedure, accomplished via implantation of boron ions through a thin silicon oxide gate insulator layer.
It is another object of this invention to subject the silicon oxide gate insulator layer to an ammonium peroxide mixture, (APM), after the threshold adjust ion implantation procedure, to reduce the surface roughness of the silicon oxide gate insulator layer, resulting from the threshold adjust ion implantation procedure.
In accordance with the present invention a method of forming CMOS devices, featuring a process used to reduce the surface roughness of a silicon oxide gate insulator, subjected to an ion implantation procedure, is described. After thermally growing a silicon oxide layer, to be used for a gate insulator layer for both NMOS and PMOS devices, boron ions are implanted through the silicon oxide gate insulator region, into the semiconductor substrate, forming threshold adjust regions for both subsequent NMOS and PMOS devices. A solution of an ammonium peroxide mixture is then used to reduce the roughness of the silicon oxide gate insulator, which was generated as a result of the boron ion, threshold adjust implantation procedure. Formation of subsequent features, such as gate structures, lightly doped source/drain regions, and heavily doped source/drain regions, are accomplished via conventional photolithographic procedures in which the needed thickness of photoresist coatings is minimized as a result of the underlying smooth silicon oxide surface.
REFERENCES:
patent: 3925107 (1975-12-01), Gdula et al.
patent: 5393686 (1995-02-01), Yeh et al.
patent: 5504022 (1996-04-01), Nkanishi et al.
patent: 5922136 (1999-07-01), Huang
patent: 5926741 (1999-07-01), Matsuoka et al.
patent: 02000243699 (2000-09-01), None
Chen Chie-Chi
Pan Sheng-Liang
Ackerman Stephen B.
Bowers Charles
Nguyen Thanh
Saile George O.
Taiwan Semiconductor Manufacturing Company
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