4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Jonathan H. Schafer

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Block connector splitting in logic block of a field...

Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate

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Block symmetrization in a field programmable gate array

Electronic digital logic circuitry – Multifunctional or programmable – Array
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Field programmable digital signal processing array...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
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Method of reducing test time for NVM cell-based FPGA

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Methods for errors checking the configuration SRAM and user...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Profile ID: LFUS-PAI-P-2035572

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