Method of reducing metal voidings in 0.25 .mu.m AL interconnect

Details Method of reducing metal voidings in 0.25 .mu.m AL interconnect Method of reducing metal voidings in 0.25 .mu.m AL interconnect

1998-05-22

2000-11-07

Niebling, John F.

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438435, 438437, 438778, 438787, 438788, 438791, 438792, H01L 2176, H01L 21469

Patent

active

061436720

ABSTRACT:
In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structure

REFERENCES:
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patent: 5549786 (1996-08-01), Jones et al.
patent: 5621241 (1997-04-01), Jain
patent: 5654589 (1997-08-01), Huang et al.
patent: 5674781 (1997-10-01), Huang et al.
patent: 5691573 (1997-11-01), Avanzino et al.

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