Method of preventing misalignment of selective silicide layer in

Details Method of preventing misalignment of selective silicide layer in Method of preventing misalignment of selective silicide layer in

2000-02-03

2000-12-19

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 438279, 438299, 438592, 438453, 257365, 257412, H01L 218242, H01L 21336

Patent

active

061626759

ABSTRACT:
A semiconductor device and a method of making the semiconductor device are disclosed. The semiconductor device includes a substrate having at least one gate electrode, the gate electrode having lateral walls and edges. Spacers are formed on the lateral walls of the gate electrode, and active areas are formed inside the substrate at the edges of the gate electrode. A DRAM cell forming part is disposed on a portion of the substrate, and includes at least one gate electrode and an active area, and a logic forming part is disposed on another portion of the substrate, and includes at least one gate electrode and an active area. The device further includes a silicide blocking layer disposed at the active area of the DRAM cell forming part, and a silicide layer formed on at least one gate electrode of the DRAM cell forming part, and on a gate electrode and the active area of the logic forming part. The method is simplified and provides selective silicidation of a highly integrated DRAM and an embedded DRAM where the DRAM cell forming part and the logic forming part are merged.

REFERENCES:
patent: 6015748 (2000-01-01), Kim et al.

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