Method of planarizing a semiconductor device by depositing a die

Details Method of planarizing a semiconductor device by depositing a die Method of planarizing a semiconductor device by depositing a die

1997-12-23

2000-12-05

Smith, Matthew

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438760, 438761, H01L 214763

Patent

active

061566373

ABSTRACT:
A method of depositing a dielectric ply structure to optimize the planarity of electronic devices that include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. In accordance with the principles of the present invention, the plurality of bit lines may be isolated from one another by the dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited. The resulting planarization avoids the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces upon which the conductive layer is deposited.

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