Method of pattern etching a low K dielectric layer

Details Method of pattern etching a low K dielectric layer Method of pattern etching a low K dielectric layer

2000-04-14

2001-12-18

Baxter, Janet (Department: 1752)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S313000, C430S311000

Reexamination Certificate

active

06331380

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method for etching of patterned layers. The method is useful in high temperature etch processes where the layers are high temperature masking materials or are metal-comprising layers such as copper, platinum, iridium, and barium strontium titanate. The method is also useful in lower temperature etch processes in which organic polymeric layers, such as low k dielectrics, are etched to form damascene process structures. The present method may also be used for lower temperature etching of metal layers such as aluminum or tungsten, when the pattern geometry is small (less than about 0.25 &mgr;m) and etch selectivity is a problem.
2. Brief Description of the Background Art
In the field of semiconductor device fabrication, particularly with the continuing trend toward smaller device feature sizes, the etch processes which are used to construct conductive features such a metal interconnects and contacts have become particularly critical. The new devices, having feature sizes in the range of about 0.25 &mgr;m and smaller, place an emphasis on both the precise profile achievable during pattern etching and on the avoidance of any residue remaining after etch which causes problems during subsequent processing or problems in long term device function.
We previously worked to develop a plasma etching system which reduces and avoids the formation of residue on the surface of a copper layer during pattern etching of the copper. The etching systems useful in etching of the conductive material are described in copending application Ser. Nos. 08/891,410, filed Jul. 9, 1997, and 08/911,878, filed Aug. 13, 1997, both of which are hereby incorporated by reference and both of which are assigned to the assignee of the present application.
We have simultaneously been working to develop an etching process which permits the development of patterning masks which can transfer a desired pattern to adjacent layers in a manner which reduces or avoids the formation of mask residue on the etched structure. Further, we have worked to develop an etching process useful in etching organic polymeric materials for damascene processes, where the conductive layer is applied over the patterned surface of a dielectric layer to form desired conductive interconnect and contact structures.
FIGS. 1A-1E
show a schematic cross-sectional view of a typical plasma etch stack for etching a metal-comprising layer at temperatures in excess of about 150° C. as it progresses through a series of steps including the etching of both dielectric and conductive layers. This etch stack is of the kind known and used prior to the present invention.
FIG. 1A
shows a complete etch stack, including, from bottom to top, Substrate
102
, which is typically a dielectric layer overlying a semiconductor substrate (such as a silicon wafer substrate) or which may be the semiconductor material itself, depending on the location on a given device surface. Barrier layer
104
, which prevents the diffusion and/or migration of material between conductive layer
106
and substrate
102
; conductive layer
106
, which is typically aluminum or copper, but might be tungsten, platinum, or iridium, for example. Anti-reflective-coating (ARC) layer
108
, which is typically a metal-containing compound and which enables better imaging of an overlying patterning layer. Pattern masking layer
110
, which is typically a layer of silicon dioxide or similar inorganic material which can withstand the high temperatures encountered during etching of conductive layer
106
, and which can be patterned and used as a mask during such etching. And, photoresist layer
112
which is typically an organic-based material which is stable at low temperatures and which is used to pattern masking layer
100
, which is stable at higher temperatures. In
FIG. 1A
, photoresist layer
112
has already been patterned to provide the feature shape desired to be transferred to pattern masking layer
100
.
FIG. 1B
shows the stack described in
FIG. 1A
, where the pattern in photoresist layer
112
has been transferred to pattern masking layer
110
, using a standard plasma etching technique. When masking layer
110
comprises a silicon-containing material, such as silicon dioxide, the etch plasma typically comprises a fluorine-generating species. Preferably the plasma selectivity is for the silicon dioxide over the photoresist material.
FIG. 1C
shows the next step in the process of etching conductive layer
106
, where the photoresist layer
112
has been stripped from the surface of pattern masking layer
110
. This stripping procedure may be a wet chemical removal or may be a plasma etch which is selective for the photoresist layer
112
over the pattern masking layer
110
. Stripping of photoresist layer
112
is carried out for two reasons. The organic-based photoresist materials typically used for layer
112
would melt or become distorted in shape at the temperatures commonly reached during the etching of conductive layer
106
. This could lead to distortion of the pattern which is transferred to conductive layer
106
. In addition, polymeric species generated due to the exposure of the surface of photoresist layer
112
to the etchant plasma tend to contaminate adjacent surfaces during the etching of conductive layer
106
, thereby decreasing the etch rate of conductive layer
106
.
The procedure of using a photoresist material to pattern an underlying silicon oxide patterning layer is described in U.S. Pat. No. 5,067,002 to Zdebel et al., issued Nov. 19, 1991. Zdebel et al. mention the need to remove the photoresist material prior to etching of underlying layers, to avoid contamination of underlying surfaces with the photoresist material during etching of such underlying layers. David Keller describes the use of an ozone plasma for the purpose of dry etch removal of a photoresist mask from the surface of an oxide hard mask in U.S. Pat. No. 5,346,586, issued Sep. 13, 1994. Mr. Keller also mentions that it is easier to etch selectively to a gate oxide when there is no photoresist present during a polysilicon gate oxide etch step.
FIG. 1D
shows the next step in the etching process, where the desired pattern has been transferred through ARC layer
108
, conductive layer
106
, and barrier layer
104
. Typically all of these layers are metal comprising layers, and a halogen containing plasma can be used to etch the pattern through all three layers. At this point, the problem is the removal of the residual silicon dioxide hard masking material and the removal of residue deposits of the silicon dioxide masking material from adjacent surfaces. The residual hard masking material is present as residual masking layer
110
, and the residue deposits as
114
on the surface of the patterned conductive layer
106
and the surface of substrate
102
.
In the case of the deposit
114
on the surface of patterned conductive layer
106
, deposit
114
can trap residual chemical etch reactants under deposit
114
and against the surface of patterned conductive layer
106
, leading to subsequent corrosion of conductive layer
106
. That corrosion is shown on
FIG. 1D
as
116
.
In addition, when substrate
102
is a low dielectric constant material, for purposes of reducing electrical interconnect delays, residual masking layer
110
which remains after pattern etching through layers
108
,
106
, and
104
(as shown in
FIG. 1D
) can deteriorate device performance or cause difficulties in future processing steps (particularly during contact via etch). This makes it important to remove any residual masking layer
110
from the surface of ARC layer
108
.
Further, when a dielectric layer
118
is applied over the surface of the patterned conductive layer
106
, as shown in
FIG. 1E
, if residual masking layer
110
is not removed, a non-planar surface
120
is produced. A non-planar surface creates a number of problems in construction of a multi-conductive-layered device, where additional patterned conductive layers

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