Method of packaging a semiconductor device with minimum bonding

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

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Details

257695, 257784, H01L 2348, H01L 2352, H01L 2940

Patent

active

056843321

ABSTRACT:
A package for a semiconductor die having a plurality of bonding pads about its periphery is provided. The package has a plastic molding encapsulating the semiconductor die. The package also has a plurality of conductive leads with leads having inner and outer portions, the inner portions encapsulated in the molding and arranged substantially in a plane and radially about the semiconductor die with ends displaced from and forming a rectangle with four corners about the die. A bonding wire extends from each of the bonding pads to one of the inner portions of the leads. Bonding wire loop heights of approximately 8 mils are made with a specially designed tip of a capillary tool. The package also has a pair of leads with inner portions at opposite corners of the rectangle, each of the inner portions connected to a pair of bonding wires from a pair of contiguous bonding pads on the die. This double wiring arrangement prevents wire sweep during the injection molding step. Bonding pad pitches of 4 mils or less on the semiconductor die are possible.

REFERENCES:
patent: 4403240 (1983-09-01), Seki et al.
patent: 4875138 (1989-10-01), Cusack
patent: 5045919 (1991-09-01), Nagaoka
patent: 5359227 (1994-10-01), Lange et al.
patent: 5550087 (1996-08-01), Brossart

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