Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1997-07-02
2000-01-18
Kunemund, Robert
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438425, 438431, 438435, 438750, H01L 21302
Patent
active
060157577
ABSTRACT:
A new method for planarization of shallow trench isolation is disclosed by using a polysilicon layer to prevent trench formed in a silicon nitride layer. The formation of the shallow trench isolation described herein includes a pad layer and a silicon nitride layer formed on a semiconductor wafer. A polysilicon layer is subsequently formed on the silicon nitride layer. A shallow trench is then created by photolithography and dry etching processes. The photoresist is subsequently removed in which an oxide layer is form in the shallow trench and on polysilicon layer for the purpose of isolation. A selective etching is used to etch the oxide layer. A CMP is performed to produce a planarized surface on a silicon wafer.
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Lee Kuei-Ying
Tao Hun-Jan
Tsai Chia-Shiung
Goudreau George
Kunemund Robert
Taiwan Semiconductor Manufacturing Co. Ltd.
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