Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-05
2003-07-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06587982
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to advanced flash IC (integrated circuit) chips which includes a state machine for performing built-in self-test functions. More particularly, the present invention relates to a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through the BIST tests.
As is generally well-known, flash IC chips have become widely used in almost all forms of electronic devices such as cell-phones, digital camera, computers, PDA and many others. As flash memory IC chips are being used more and more, there has been a growing trend of requiring increased demands from flash designers in many characteristics of the flash manufacturing processes, such as reliability.
For example, since these flash IC chips are quite complex in nature, flash chips manufacturers have to manually test these chips before they are being shipped to customers. This process of manual testing is tedious and requires much effort. Not to mention the high cost involved. With this in mind, flash chips manufacturers have implemented a method of built-in self-test circuitry on the flash memory IC chip so as to perform internal hardware tests on the various types of integrated circuits associated with the flash chip before they are shipped to the customers. This built-in self-test would make all the necessary tests on its own with only a minimal external hardware and minimal manual supervision. This capability of having built-in self-test circuitry eliminates the need of expensive hardware testers which greatly increases the overall manufacturing cost.
In our co-pending application Ser. No. 09/655,335 filed on Sep. 5, 2000 and entitled “Method of Micro-Architectural Implementation on BIST Frontend state Machine Utilizing ‘Death Logic’ State Transition for Area Minimization”, there is illustrated and described a BIST state machine that can be used to perform the BIST test automatically. This Ser. No. 09/655,335 is assigned to the same assignee as the present invention and is hereby incorporated by reference in its entirety. The tester interface circuit of the instant invention can be used to interface with such BIST state machine so as to perform the BIST tests automatically.
In order to perform the BIST tests automatically, there is required a tester interface circuit which can accept the necessary protocols being loaded in by a user, such as a test engineer. Upon identifying the necessary protocols, the BIST state machine is caused to cycle through the required BIST tests dependent upon the data being loaded into the tester interface circuit through the BIST protocols. Therefore, it would be desirable to a tester interface circuit which is closely linked to the BIST state machine so as to operate on an effective and efficient basis. Further, it would be expedient to implement the tester interface circuit with a minimum amount of chip area on a semiconductor IC.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through the BIST tests.
It is another object of the present invention to provide a tester interface circuit for use with a BIST state machine which is achieved with a minimal amount of chip area on a semiconductor IC.
It is another object of the present invention to provide a tester interface circuit which is closely linked to the BIST state machine so as to operate on an effective and efficient basis.
It is still another object of the present invention to provide a tester interface circuit for use with a BIST state machine which includes a logic decoder for determining which particular register in a shift register is to be set or cleared in response to status signals from the BIST state machine.
In a preferred embodiment of the present invention, there is provided a tester interface circuit for use with a BIST state machine so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and polling logic device. The storage device stores data that is inputted by a user and generates output register signals corresponding to which tests are to be executed by the BIST state machine. The logic decoder is responsive to status signals from the BIST state machine for determining which particular register in a shift register is to be set or cleared.
The set/clear mechanism is responsive to a completed signal indicating that a particular test has been completed, a failed signal indicating that a particular test has failed, and a pass signal indicating that a particular is to be bypassed for generating a set/clear signal. The shift register is formed of a plurality of registers and is responsive to the logic decoder and the set/clear signal for storing the result of the test currently being executed. The polling logic device is responsive to a busy signal for indicating that a test is currently being executed and that the BIST state machine is busy.
REFERENCES:
patent: 5668815 (1997-09-01), Gittinger et al.
patent: 5872793 (1999-02-01), Attaway et al.
patent: 6044481 (2000-03-01), Kornachuk et al.
Bautista Edward V.
Bill Colin S.
Halim Azrul
Lee Weng F.
Pan Feng
Advanced Micro Devices , Inc.
Chase Shelly A
Chin Davis
De'cady Albert
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