Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2009-05-31
2011-12-20
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000
Reexamination Certificate
active
08082477
ABSTRACT:
The present invention discloses a memory build-in self-test comprising steps of: (a) determining whether there is redundant address in the ROM; (b) when there is redundant address for storing standard check code, transferring the coefficient file in the ROM to a predetermined format; (c) producing a self-test logic and a standard check code corresponding to the ROM via design tool; (d) writing the standard check code into the redundant address and generating a new ROM. The present invention can assure that the standard check code and coefficient can be simply revised via corresponding way of Mask Change, so as to detect the damages of ROM by using memory build-in self-test (MBIST) which does not need to remake a whole set of Mask to revise the standard check code outside the ROM, so as to save cost and time, and lower the difficulty to update the product.
REFERENCES:
patent: 5091908 (1992-02-01), Zorian
patent: 7441165 (2008-10-01), Tseng et al.
patent: 2004/0193984 (2004-09-01), Soundron
patent: 2006/0090105 (2006-04-01), Woods
Tang Dujuan
Yang Xiu
IPGoal Microelectronics (SiChuan) Co., Ltd.
Ton David
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