Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-15
2005-02-15
Pham, Hoai (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S231000
Reexamination Certificate
active
06855590
ABSTRACT:
A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.
REFERENCES:
patent: 4949136 (1990-08-01), Jain
patent: 5015595 (1991-05-01), Wollesen
patent: 6670251 (2003-12-01), Fukada et al.
Kim Moo-Sung
Lee Han-Sin
Park Seung-Hyun
Seo Sang-Hun
Yang Won-Suk
Lee & Sterba, P.C.
Pham Hoai
Samsung Electronics Co,. Ltd.
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