Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-01-30
2004-11-30
Pham, Hoai (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S253000
Reexamination Certificate
active
06825076
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-38550, filed in Feb. 15, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a ferroelectric capacitor and a method of manufacturing the same.
2. Description of the Prior Art
As the nonvolatile memory that still stores the information when the power supply is turned off, the ferroelectric random access memory (FeRAM) is known.
The FeRAM has a memory cell that stores the information using the hysteresis characteristic of the ferroelectric capacitor. The ferroelectric capacitor has the structure in which a ferroelectric film is formed between a pair of electrodes. In the ferroelectric capacitor, the polarization is generated in response to the magnitude of the voltage applied between the electrodes, and the spontaneous polarization is kept even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Then, the information can be read by sensing the spontaneous polarization.
As the FeRAM memory cell, the 1T/1C type that uses one transistor and one capacitor to store 1-bit information and the 2T/2C type that uses two transistors and two capacitors to store 1-bit information are present. The 1T/1C type memory cell can reduce the cell area and achieve the higher integration in contrast to the 2T/2C type memory cell.
Next, steps of forming the 1T/1C type memory cell having the stacked capacitor is explained hereunder.
First, steps required to get a structure shown in
FIG. 1A
is explained.
An element isolation insulating film
102
is formed around an element forming region of a silicon substrate
101
, and then a well
103
is formed in the element forming region. Then, two MOS transistors
104
are formed in the well
103
.
The MOS transistor
104
has a gate electrode
104
b
formed on the well
103
via a gate insulating film
104
a
, and impurity diffusion regions
104
c
,
104
d
formed in the well
103
on both sides of the gate electrode
104
b
and serving as source/drain regions. Also, insulating sidewalls
105
used to form high impurity concentration regions
104
d
in the impurity diffusion regions
104
c
are formed on both side surfaces of the gate electrode
104
b.
Then, a transistor protection insulating film
106
for covering the MOS transistors
104
is formed on the silicon substrate
101
, and then a first interlayer insulating film
107
is formed on the transistor protection insulating film
106
.
Then, first contact hole
107
a
are formed in the first interlayer insulating film
107
on one impurity diffusion regions
104
c
of the MOS transistors
104
, and then first contact plugs
108
are buried in the first contact hole
107
a.
Then, a first metal film
109
, a ferroelectric film
110
, and a second metal film
111
are formed sequentially on the first contact plugs
108
and the first interlayer insulating film
107
.
Then, as shown in
FIG. 1B
, capacitors
112
are formed by patterning the first metal film
109
, the ferroelectric film
110
, and the second metal film
111
by virtue of the photography method. In the capacitor
112
, the first metal film
109
is used as a lower electrode
109
a
, the ferroelectric film
110
is used as a dielectric film
110
a
, and the second metal film
111
is used as an upper electrode
111
a
. The capacitor
112
is the stacked type capacitor, and the lower electrode
109
a
is connected to one impurity diffusion layer
104
c
of the MOS transistor
104
via the underlying first contact plug
108
.
Then, as shown in
FIG. 1C
, a single-layer capacitor protection film
113
is formed only once on the capacitors
112
and the first interlayer insulating film
107
, then a second interlayer insulating film
114
is formed on the capacitor protection film
113
, and then a second contact hole
114
a
is formed on the other impurity diffusion region
104
d
of the MOS transistors
104
by patterning the second interlayer insulating film
114
, the capacitor protection film
113
, the first interlayer insulating film
107
, and the transistor protection insulating film
106
by virtue of the photolithography method. Then, a second contact plug
115
is formed in the second contact hole
114
a.
Next, steps required to form a structure shown in
FIG. 1D
will be explained hereunder.
Third contact holes
114
b
are formed on the upper electrodes
110
a
of the capacitors
112
by patterning the second interlayer insulating film
114
. Then, a conductive film is formed on the second interlayer insulating film
114
and in the third contact holes
114
b
. Then, this conductive film is pattern to form wirings
116
a
, which are connected to the upper electrodes
111
a
of the capacitors
112
, and at the same time to form a conductive pad
116
b
on the second contact plug
115
.
Then, a third interlayer insulating film
117
for covering the wirings
116
a
and the conductive pad
116
b
is formed on the second interlayer insulating film
114
. Then, a hole
117
a
is formed on the conductive pad
116
b
by patterning the third interlayer insulating film
117
, and then a fourth conductive plug
118
is formed in the hole
117
a.
Then, a bit line
119
that is connected to the conductive plug
118
is formed on the third interlayer insulating film
117
.
An arrangement of the MOS transistors, the capacitors, and the word line in the 1T/1C type memory cell, as described above, is given in a plan view of FIG.
2
. In this case,
FIG. 1D
is a sectional view taken along a I—I line in FIG.
2
.
By the way, when the second contact hole
114
a
is opened in the first and second interlayer insulating films
107
,
114
, the alignment margin is required to prevent the contact of the second contact hole
114
a
to the capacitors
112
. In this case, the second contact hole
114
a
must be separated from the capacitors
112
to such extent that the alignment margin can be assured. Accordingly, an interval between two capacitors
112
that are positioned adjacently over the well
103
is decided.
Unless such alignment margin is assured, it is possible that the second contact hole
114
a
overlaps with a part of the capacitors
112
.
If the second contact hole
114
a
is formed to come into contact with the capacitors
112
, the second contact plug
115
in the second contact hole
114
a
is short-circuited to the capacitors
112
. Also, if the second contact hole
114
a
comes into contact with the capacitors
112
, there is a possibility that, when the second contact plug
115
is formed by the CVD method, the ferroelectric film
110
is reduced by the reaction gas and thus the ferroelectric film
110
of the capacitor is degraded.
Also, if the area of the capacitor
112
is reduced to achieve the higher integration of the memory cell, the memory cell characteristic is ready to degrade.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a structure that is capable of reducing an alignment margin of a contact hole formed next to a capacitor, and a method of manufacturing the same.
The above subjects can be overcome by providing a semiconductor device that comprises a first impurity diffusion region formed in a semiconductor substrate; a first insulating layer formed over the semiconductor substrate; a capacitor formed on the first insulating layer and having a lower electrode, a ferroelectric layer, and an upper electrode; an insulating capacitor protection layer made of material that is different from the first insulating layer, for covering an upper surface and a side surface of the capacitor; a second insulating layer formed on the capacitor protection layer and the first insulating layer, and made of material that can be etched selectively
Pham Hoai
Westerman Hattori Daniels & Adrian LLP
LandOfFree
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