Method of manufacturing stacked capacitors in a DRAM with reduce

Details Method of manufacturing stacked capacitors in a DRAM with reduce Method of manufacturing stacked capacitors in a DRAM with reduce

1996-09-10

1998-08-25

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, H01L 218242

Patent

active

057982899

ABSTRACT:
A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

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