Method of manufacturing split gate flash memory device

Details Method of manufacturing split gate flash memory device Method of manufacturing split gate flash memory device

2003-07-31

2004-10-05

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C438S267000

Reexamination Certificate

active

06800525

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a non-volatile memory device; and more particularly, to a method of manufacturing a flash memory device having a split gate.
2. Description of the Related Art
Recently, a split gate flash memory device is manufactured in such a way that a floating gate and a control gate are split. The device is commonly used as a portable data storage device.
A prior art manufacturing method of such a split gate flash memory device is disclosed in the thesis of Rebecca Mih, entitled, “0.18 um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” (2000 Symposium on VLSI Technology Digest of Technical Papers. pp. 120-121, 2000).
In fabricating such a split gate flash memory device, resistance of a word line may be high, and a short between the word line and a drain junction region may be caused.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method of fabricating a split gate flash memory device, which is capable of reducing resistance of a word line.
Another object of the present invention is to provide a method of fabricating a split gate flash memory device, which is capable of preventing a short between a word line and a drain junction region.
To achieve these objects, and in one aspect of the present invention, the method of manufacturing a split gate flash memory device comprises the steps of: (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region, the semiconductor substrate being provided with a floating gate, a first spacer surrounding the floating gate, the first junction region of a constant conductivity type, which is overlapped with the first spacer and is formed on the substrate, and a first conductive line contacted with the first spacer and formed on the first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) planarizing the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) planarizing the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film, and exposing the first conductive film provided in a lower part thereof; (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask so as to form a second gate dielectric film and a word line; (i) forming a second spacer on a sidewall of the word line; (j) forming a second junction region of a conductivity type the same as that of the first junction region on the substrate, the second junction region being overlapped with the word line and the second spacer; (k) forming an interlayer dielectric film having a contact hole for exposing the second junction region, on an entire upper face of the substrate; and (l) forming a second conductive line contacted with the second junction region through the contact hole.
It is desirable in step (c) to remove the third dielectric film by a given thickness through a chemical mechanical polishing (CMP) process until the second dielectric film is exposed. It is also desirable in (e) to remove the second dielectric film and the first conductive film by a constant thickness through an etching process.
The third dielectric film is preferably formed as a buffer layer in the CMP process in order to improve step coverage of the first conductive film. It is desirable that the third dielectric film is an HDP film, a TEOS film, or a USG film.
The second dielectric film is a stopper layer in the CMP process performed in step (c), and preferably is the film to protect the first conductive film provided in a lower part thereof, from the etching process executed in step (e).
Preferably, the first junction region is a source junction region, the second junction region is a drain junction region, the first conductive line is a source line made of polysilicon, and the second conductive line is a metallic line.
In step (f), the fourth dielectric film preferably is an oxidation film that is selectively formed through an oxidation process in which the second dielectric film is used as a mask.
The word line has a uniform width and a sidewall of a vertical structure contacted with the second spacer.
According to another aspect of the present invention, the method of manufacturing a split gate flash memory device comprises the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region, the semiconductor substrate being provided with floating gates spaced from each other, first spacers respectively surrounding the floating gates, the first junction region of a constant conductivity type, which is overlapped with the first spacers and is formed on the substrate, and a first conductive line contacted with the first spacer and formed on the first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) planarizing the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) planarizing the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film, and exposing the first conductive film provided in a lower part thereof; (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask, and forming a second gate dielectric film and a word line; (i) forming a second spacer on a sidewall of the word line; (j) forming a second junction region of a conductivity type the same as that of the first junction region on the substrate, the second junction region being overlapped with the word line and the second spacer; (k) forming an interlayer dielectric film having a contact hole for exposing the second junction region on an entire upper face of the substrate; and (l) forming a second conductive line contacted with the second junction region through the contact hole.
With respect to still another aspect of the present invention, the method of manufacturing a split gate flash memory device includes the steps of forming, on a semiconductor substrate, a first conductive film, and sequentially forming a first dielectric film and a second dielectric film which serve as a buffer in planarizing the first conductive film in a subsequent step, and then planarizing the second dielectric film, the first dielectric film and the first conductive film till a first conductive line is exposed, wherein the semiconductor substrate is provided with a floating gate, a first spacer surrounding the floating gate, a first junction region of a constant conductivity type, which is overlapped with the first spacer and is formed on the substrate, and the first conductive line contacted with the first spacer and formed on the first junction region; and forming a word line by etching the first conductive film.


REFERENCES:
patent: 6524915 (2003-02-01), Kim et al.
patent: 6541324 (2003-04-01), Wang
Mih, R., “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” 2000 Symposium on VLSI Technology Digest of

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