Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2003-04-21
2004-10-05
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S030000, C326S090000, C327S108000, C710S100000, C710S120000
Reexamination Certificate
active
06801054
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to an output buffer for sending data signals, and more particularly to an output buffer suitable for use in high-speed data transfer.
BACKGROUND OF THE INVENTION
In recent years the operation speeds of central processing units (CPUs), and the like, have continued to increase. As a result, in computer systems and the like, the speed at which data must be transferred between semiconductor devices, or printed circuit boards containing such devices, has also increased. To meet such higher data transfer speeds, high speed transmission line structures are typically employed. For example, a motherboard can include micro-striplines for transmitting data signals, or coaxial cables are included for connecting circuits on a printed circuit boards, or for connecting to printed circuit boards.
In the case of low frequency signals having relatively low data transmission rates, a signal wavelength can be much longer than a transmission line length. Thus, a signal phase can be nearly identical on all portions of the transmission line at a given time. As a result, even if noise is generated by signal reflection arising from impedance mismatch, because such noise is in phase with the signal, the signal waveform is not substantially deteriorated.
However, in the case of a high frequency signal, a signal waveform may become much shorter than the length of a transmission line. Thus, a signal phase varies according to the particular portion of the transmission line. As a result, the phase at which reflected noise affects the transmitted signal may not be known, and it can be possible for the reflected noise to significantly deteriorate signal quality.
One general way to address the above drawbacks for high frequency signals can be termination processing. Termination processing can include providing an impedance at a signal matching end or signal transmission end that matches a characteristic impedance of the transmission line. This can suppress noise generated by reflected signals.
FIG. 6
is a circuit diagram showing one example of a parallel termination arrangement made on a signal reception end.
FIG. 7
is a circuit diagram showing one example of a series (or serial) termination made on a signal transmission end.
Referring now to
FIG. 6
, in a parallel termination arrangement a signal receiving end can be connected to a power supply voltage or ground potential through a resistor (terminal or terminating resistor). A terminal resistor can have an impedance equal to a characteristic impedance of the transmission line. In contrast, in the series termination arrangement of
FIG. 7
, a number of driver circuits (i.e., n driver stages, where n is a positive integer) can be arranged at a signal transmission end and operated in parallel. Each driver stage includes a p-channel metal-oxide-semiconductor field effect transistor (MOSFET) and an n-channel MOSFET. A resulting output impedance of such driver stages can made to equal a characteristic impedance of a transmission line.
The above parallel termination arrangement for a signal reception end is adapted for use with a high speed bus, as signal reflection can be reduced or eliminated. However, in such an arrangement a reception end can be connected to a power supply voltage (or ground potential) through a terminal resistor. Thus, a signal voltage is divided with an output impedance of a signal transmission side and the terminal resistor. As a result, a signal amplitude is decreased in order to increase noise margin. In addition, in the above parallel termination arrangement, a current will flow between a power supply voltage and ground potential through a terminal resistor, which may have a relatively low resistance. This can result in increased power consumption. Still further, adding a terminal resistor to various inputs can increase a resulting cost of a device.
In the case of a series termination made on a signal transmission side, because an output impedance can be made to match a characteristic impedance of a transmission line, there is no need to provide a terminal resistor. Thus, a signal transmission side can provide reduction in noise while at the same time preventing power consumption resulting from a terminal resistor. However, signal transmission side termination can have drawbacks, as signals reflected on a reception side are terminated on the transmission side. Consequently, if a series termination is applied to a bus arrangement, it can take more time to transfer a signal, as one portion of a bus can be closer to a signal transmission end. That is, a signal will have to make a round trip through an entire bus-type transmission line between the transmission of the signal and reception of the corresponding reflected signal.
In one-to-one communication, signal transmission sides can have a one-to-one correspondence with a signal reception. Thus, in such arrangements it is preferable to provide series termination on a signal transmission side, as this can reduce power consumption and reduce noise margin, as noted above.
To better understand the invention, an example of a conventional series termination arrangement, configured for one-to-one communication, will now be described.
Referring now to
FIG. 8
, an eye diagram is set forth showing a data transfer waveform for a conventional series termination arrangement.
In recent years, high speed data transfer interfaces have utilized a data reception circuit that includes an input buffer circuit with a differential amplifier circuit that meets the series stub terminated logic (SSTL) standard. In such an input buffer circuit, the level of a received signal is judged with respect to a reference voltage Vref (normally, Vref=Vdd/2). Received data can be pulse shaped, and the input buffer circuit can provide an output signal according to such a comparison with a reference voltage Vref level.
However, a reference voltage Vref provided to an input buffer circuit may vary (from Vref+ to Vref−) due to uncontrollable conditions, such as ambient temperature, for example. Thus, to improve the stability of data reception, it is preferable that in a response like that of
FIG. 8
, an opening in the eye diagram be made as large as possible.
A first conventional series termination arrangement is shown by waveform
800
. Waveform
800
shows how a series termination arrangement can provide a low noise response, hence the width of the signal can be relatively narrow. However, such an arrangement can have drawbacks. When an output impedance of an output buffer is made to match the characteristic impedance of a transmission line, a driving ability of such a circuit can be restricted. This results in the rise/fall time (referred to herein as the AC performance) of a driven pulse signal being lengthened. Consequently, if a desired data transfer rate is relatively high, it can be impossible to provide a response with a sufficiently large opening when represented by an eye diagram.
An output impedance of an output buffer can be reduced to thereby increase driving ability. This can shorten rise/fall times with respect to an impedance matched output buffer circuit. However, because a signal transmission end is no longer terminated with a matching impedance, reflected noise is generated, increasing a jitter component of a response. Such a second conventional arrangement is shown by waveform
802
. As shown, additional noise an result in a waveform
802
of increased width when represented by an eye diagram.
In light of the above, it would desirable to provide an output buffer circuit that can have enhanced AC performance and noise suppression with respect to conventional approaches. Such an arrangement can result in a response that presents an enlarged opening when represented by an eye diagram.
SUMMARY OF THE INVENTION
The present invention may include an output buffer circuit for sending output data signals on a transmission line according to input data signals supplied from an internal circuit. The output buffer circuit can include a pluralit
NEC Electronics Corporation
Sako Bradley T.
Tan Vibol
Walker Darryl G.
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