Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-20
2002-02-26
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000
Reexamination Certificate
active
06350642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing various metal contact studs suitable for various purposes simultaneously during the same fabrication step.
2. Description of the Related Art
As the integration of semiconductor devices such as dynamic random access memories (DRAMs) increases, the design rule becomes smaller and hence the margin or spatial tolerance for photolithography decreases. To alleviate problems with the reduction in design rule and photography margin, a capacitor over bit line (COB) structure and a multi-layer metallization structure have been adopted. However, since the height of a capacitor increases with the reduction in the design rule, the step difference between a region on which the capacitor is formed and a region on which the capacitor is not formed, that is, between cell and core or peripheral regions, becomes increasingly larger.
Thus, to make electrical interconnections in wiring lines formed on the uppermost surface of a semiconductor device, it is highly desirable to have a semiconductor device having metal contact studs having various heights. That is, the contact studs may be formed so as to connect with the bit line, contact or connect with an active region formed on a semiconductor substrate, or connect with the gate of a transistor. Also, the metal contact studs may be formed so as to contact or connect with a plate electrode of the capacitor.
Conventionally, to form various metal contact studs suitable for their purposes, a very complicated fabrication process is required. Furthermore, the size of each metal contact becomes significantly smaller due to the reduction in design rule, which makes the manufacturing process of the metal contact studs more difficult.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a method of manufacturing a semiconductor device including various stack studs that can overcome problems with the reduction in design rule and large step difference while simplifying the overall fabrication process.
In accordance with the invention, there is provided a method of manufacturing a semiconductor device. According to the method of the invention, a first interlayer dielectric layer which surrounds and insulates a plurality of conductive plugs is formed on a semiconductor substrate such that the top surfaces of the plurality of conductive plugs are exposed. A bit line electrically connected to a first conductive plug is formed on the first interlayer dielectric layer. The bit line includes at least one spacer on the sidewall of the spacer. A capping insulating layer is formed at one portion of the top surface of the bit line, and a first etch stop pattern having a thickness smaller than the capping insulating layer is formed at another portion of the top surface. A second etch stop pattern is formed to cover the surface of a second conductive plug. A second interlayer dielectric layer that overlies the capping insulating layer and the first and second etch stop patterns is formed. The second interlayer dielectric layer is etched using the first and second etch stop patterns as an etch stop point to form a plurality of contact holes aligned to the bit line and the second conductive plug, respectively. Portions of the first and second etch stop pattens exposed by the plurality of contact holes are etched to expose the top surfaces of the bit line and the second conductive plug. A plurality of conductive contact studs electrically connected to the bit line and the second conductive plug are formed by filling the plurality of contact holes.
In one embodiment, the second conductive plug is electrically connected to the semiconductor substrate. Alternatively, the second conductive plug can be electrically connected to a gate formed on the semiconductor substrate.
In one embodiment, while the bit line is formed, an electrode connected to a third conductive plug of the plurality of conductive plugs is also formed. A third etch stop pattern can be formed on the top surface of the electrode, and a spacer can be formed along a sidewall of the electrode.
The first etch stop pattern can be formed of at least one of silicon nitride, silicon carbide and aluminum oxide. The second etch stop pattern can also be formed of at least one of silicon nitride, silicon carbide and aluminum oxide. In one embodiment, the difference in thickness between the first and second etch stop patterns is less than 100 Å.
The first etch stop pattern can be formed by forming the capping insulating layer extending to a portion where the first etch stop pattern is positioned and by selectively etching the capping insulating layer and reducing its thickness. The method can also include forming a third interlayer dielectric layer overlying the capping insulating layer under the second interlayer dielectric layer. A lower electrode of a capacitor, a dielectric layer and an upper electrode layer can be formed on the third interlayer dielectric layer to underlie the second interlayer dielectric layer. The upper electrode layer can be patterned to form an upper electrode. The first etch stop pattern is formed by etching the third interlayer dielectric layer exposed after having patterned the upper electrode layer and by etching a portion of the capping insulating layer exposed by etching the third interlayer dielectric layer. The second etch stop pattern can be formed by patterning a spacer layer deposited on the bit line to form the spacer.
In one embodiment, the first and second etch stop patterns are formed by selectively removing the portion of the capping insulating layer overlying the portion where the first etch stop pattern will be formed and selectively exposing the top surface of the bit line while exposing the top surface of the second conductive plug. An etch stop layer is formed overlying the exposed top surfaces of the bit line and the second conductive plug, and the etch stop layer is patterned. In one more particular embodiment, a third interlayer dielectric layer is formed overlying the capping insulating layer under the second interlayer dielectric layer. A lower electrode of a capacitor, a dielectric layer and an upper electrode layer are formed on the third interlayer dielectric to underlie the second interlayer dielectric layer. The upper electrode layer is patterned to form an upper electrode. To expose the top surface of the second interlayer dielectric layer, the second interlayer dielectric layer is continuously etched after patterning the upper electrode layer. A portion of the capping insulating layer exposed by etching the third interlayer dielectric layer is etched to expose the top surface of th underlying bit line. The third interlayer insulating layer is continuously etched using the exposed bit line as an etch mask.
The present invention can prevent the occurrences of a defective profile such as the excessive loss of an interlayer dielectric layer, which underlies the contact hole, while simultaneously forming metal contact studs electrically connected to the bit line, the semiconductor substrate, or the gate.
REFERENCES:
patent: 6077742 (2000-06-01), Chen et al.
patent: 6184081 (2001-02-01), Jeng et al.
Jeon Jeong-sic
Lee Sung-choon
Min Gyung-jin
Shin Kyoung-sub
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Tsai Jey
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