Method of manufacturing semiconductor device with offset...

Details Method of manufacturing semiconductor device with offset... Method of manufacturing semiconductor device with offset...

2007-05-22

2007-05-22

Crane, Sara (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S232000, C438S303000, C438S305000

Reexamination Certificate

active

10212252

ABSTRACT:
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51–54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

REFERENCES:
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 6380021 (2002-04-01), Wang et al.
patent: 6492218 (2002-12-01), Mineji
patent: 9-167804 (1997-06-01), None
H. Sayama, et al. “80nm CMOSFET Technology Using Double Offset-Implanted Source/Drain Extension and Low Temperature SiN Process” IEEE 2000, 4 pages.
Pending U.S. Appl. No. 09/796,597, filed Mar. 2, 2001.

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