Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-09
2005-08-09
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000
Reexamination Certificate
active
06927126
ABSTRACT:
A second insulating layer is formed on a first insulating layer. A plurality of stacks each including a bit line and a bit line mask are formed on the second insulating layer. A third insulating layer is formed overlying the second insulating layer to fill gaps between the plurality of stacks. A hard mask layer is formed on the third insulating layer. A photoresist pattern is formed on the hard mask layer. The photoresist pattern has an opening region that intersects the plurality of stacks. The hard mask layer and the third insulating layer are sequentially etched, using the photoresist pattern as an etching mask, thereby forming a hard mask pattern and forming a recess in the third insulating layer. The recess exposes a portion of upper sidewalls of the bit line mask. Spacers are formed on the exposed upper sidewalls of the bit line mask.
REFERENCES:
patent: 6261964 (2001-07-01), Wu et al.
patent: 6511879 (2003-01-01), Drynan
patent: 6602773 (2003-08-01), Lee et al.
patent: 6649510 (2003-11-01), Lee
patent: 1020020088980 (2002-11-01), None
English language abstract of Korean Publication No. 1020020088980.
Hwang Yoo-Sang
Park Je-Min
Son Seung-Young
Chaudhari Chandra
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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