Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-01-17
2006-01-17
Smith, Bradley K. (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S294000, C438S238000
Reexamination Certificate
active
06987043
ABSTRACT:
A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
REFERENCES:
patent: 5866946 (1999-02-01), Kamigaki et al.
patent: 6060723 (2000-05-01), Nakazato et al.
patent: 6693041 (2004-02-01), Divakaruni et al.
patent: 5110019 (1993-04-01), None
Haga Satoru
Kisu, legal representative Haruko
Kisu, legal representative Teruo
Kujirai Hiroshi
Matsuoka Hideyuki
Antonelli, Terry Stout and Kraus, LLP.
Hitachi , Ltd.
Hitachi ULSI Systems Co., LTD
Smith Bradley K.
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