Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2005-11-22

2005-11-22

Wilson, Allan R. (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000

Reexamination Certificate

active

06967139

ABSTRACT:
In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.

REFERENCES:
patent: 5721173 (1998-02-01), Yano et al.
patent: 5851928 (1998-12-01), Cripe et al.
patent: 5945708 (1999-08-01), Tihanyi
patent: 6445113 (2002-09-01), Seko et al.
patent: 6790742 (2004-09-01), Yang et al.
patent: 11176923 (1999-07-01), None

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