Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-05-01
2001-12-04
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S223000, C438S228000, C438S232000
Reexamination Certificate
active
06326254
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having various types of semiconductor elements integrated on a single semiconductor chip.
b) Description of the Related Art
A CMOS (complementary metal-oxide-semiconductor) circuit on a single semiconductor chip of a first conductivity type requires at least a well of a second conductivity type opposite to the first conductivity type.
In order to satisfy the conditions such as separation of highly integrated fine or minute elements of a semiconductor device, some semiconductor substrates of a first conductivity type have a well of the first conductivity type and another well of a second conductivity type opposite to the first conductivity type.
FIGS. 9A-9C
and
10
A-
10
D show examples of manufacturing techniques of forming two types of wells (twin wells).
FIGS. 9A-9C
show an example of a manufacturing technique of forming n- and p-type wells on a single semiconductor substrate. In this example, a p-type semiconductor substrate is used.
Referring to
FIG. 9A
, a silicon oxide film
103
is formed on a p-type silicon substrate
101
by thermal oxidation. A silicon nitride film
105
is formed on the silicon oxide film
103
by CVD (chemical vapor deposition). A resist layer is formed on the silicon nitride film
105
, exposed and developed so as to form a resist mask
107
.
By using the resist mask
107
as an etching mask, the silicon nitride film
105
is selectively etched by dry etching so as to expose the silicon oxide film
103
.
By using the patterned resist mask
107
and silicon nitride film
105
as an ion implanting mask, boron (B) ions are implanted into the silicon substrate
101
under the exposed area of the silicon oxide film
103
so as to form a boron implanted region
121
a.
The number of processes required up to this state are five, including the oxide film forming process, nitride film forming process, mask forming process, etching process, and boron ion implanting process.
Next, as shown in
FIG. 9B
, the resist mask
107
is removed. Thereafter, by using the silicon nitride film
105
as a mask, a thick silicon oxide film
109
is formed on the exposed area of the silicon oxide film
103
by LOCOS (local oxidation of silicon).
After the LOCOS process, the silicon nitride film
105
used as the oxidation mask is removed. Then, phosphorus (P) ions are implanted under the conditions that the phosphorus ions pass through the silicon oxide film
103
and do not pass through the thick silicon oxide film
109
. As a result, a phosphorus ion implanted region
122
a
is formed only under the exposed area of the thin silicon oxide film
103
. The number of processes up to this state shown in
FIG. 9B
is four, including the resist mask removing process, oxide film forming process, nitride film removing process, and phosphorus (P) ion implanting process.
Next, as shown in
FIG. 9C
, a drive-in process for implanted impurity ions is performed by subjecting the p-type Si substrate
101
to a thermal treatment. After the drive-in process, the thin silicon oxide film
103
and thick silicon oxide film
109
are removed so that the silicon surface is exposed. The exposed silicon surface is subjected to a light thermal oxidation process to thereby form a thin silicon oxide film
111
on the silicon surface.
Next, a silicon nitride film is formed on the silicon oxide film by CVD, and a resist layer is formed on the silicon nitride film. The resist layer is then exposed and developed so as to form a resist mask. By using this resist mask as an etching mask, the silicon nitride film is selectively etched so as to form a patterned silicon nitride film
113
. Thereafter, the resist mask is removed.
The number of processes up to this state is seven, including the drive-in process of implanted impurity ions, oxide film removing process, oxidizing process, nitride film forming process, resist mask forming process, etching process, and resist mask removing process. The total number of processes explained with
FIGS. 9A-9C
is therefore sixteen.
If an oxidizing process is performed after the state shown in
FIG. 9C
, a thick silicon oxide film is selectively formed by LOCOS under the area not covered with the silicon nitride film
113
.
Another conventional manufacturing technique will be explained with
FIGS. 10A-10D
, which forms twin wells.
As shown in
FIG. 10A
, a silicon oxide film
112
is formed on the surface of a p-type silicon substrate
101
. On the silicon oxide film
112
, a silicon nitride film and a resist layer are formed. The resist layer is selectively exposed and developed so as to form a resist mask.
By using this resist mask as an etching mask, the silicon nitride film is selectively etched to form a patterned silicon nitride film
113
, and thereafter the resist mask is removed. The number of manufacturing processes up to this state shown in
FIG. 10A
is five, including the oxide film forming process, nitride film forming process, mask forming process, selective etching process, and resist removing process.
Next, as shown in
FIG. 10B
, a resist layer is formed on the surface of the silicon substrate
101
, and exposed and developed to form a resist mask
108
. By using this resist mask
108
as an ion implanting mask, boron (B) ions are implanted into the silicon substrate at the area not covered with the resist mask
108
so as to form a boron (B) ion implanted region
121
a.
The number of processes up to the state shown in
FIG. 10B
is two, including the resist mask forming process and boron ion implanting process.
Next, as shown in
FIG. 10C
, the resist mask
108
used for forming the boron ion implanted region
121
a
is removed, and a new photoresist layer is formed, exposed and developed so as to form a resist mask
109
.
By using this resist mask
109
as an ion implanting mask, phosphorus (P) ions are implanted to form a phosphorus (P) ion implanted region
122
a.
The number of processes up to this state shown in
FIG. 10C
is three, including the resist mask removing process, resist mask forming process, and phosphorous (P) ion implanting process.
Next, as shown in
FIG. 10D
, the resist mask
109
is removed and a drive-in diffusion process for implanted impurity ions is performed by heating the silicon substrate
101
. The impurity ions implanted at the processes explained with
FIGS. 10B and 10C
are diffused and activated so as to form a p-type well
121
and an n-type well
122
.
The number of processes up to the state shown in
FIG. 10D
is two, including the resist mask removing process and drive-in diffusion (well running) process. The total number of processes explained with
FIGS. 10A-10D
is therefore twelve.
With the processes explained with
FIGS. 9A-9C
and
FIGS. 10A-10D
, it is possible to form p- and n-type wells having uniform characteristics in a semiconductor substrate.
Even if p- and n-type wells having uniform characteristics are formed in a semiconductor substrate, there is a case where the requirements of a semiconductor device are not satisfied. Such a case occurs when p- and n-type wells electrically isolated from a semiconductor substrate are to be formed.
If wells electrically isolated from the substrate can be formed, the bias conditions of wells can be set independently from each other. A triple well structure has been proposed so as to form wells electrically isolated from the substrate and having the same conductivity type as that of the substrate.
In the triple well structure, on a substrate of a first conductivity type, wells of a second conductivity type opposite to the first conductivity type are formed, and wells of the first conductivity type are formed in some wells of the second conductivity type. For example, on a p-type substrate, n-type wells are formed, and p-type wells are formed in some n-type wells. With this structure, p-type wells in the n-type wells can be electrically isolated from the p-type substrate. P-type wells electrically conne
Asano Masayoshi
Ema Taiji
Kanazawa Kenichi
Katayama Masaya
Miyoshi Satoru
Armstrong, Westerman, Hattori, McClelland & Naughton, LLP
Fujitsu Limited
Trinh Michael
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