Method of manufacturing non-volatile memory device

Details Method of manufacturing non-volatile memory device Method of manufacturing non-volatile memory device

1999-09-24

2001-01-30

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S263000, C438S265000, C438S266000, C438S527000, C438S560000, C438S593000, C438S595000

Reexamination Certificate

active

06180457

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a non-volatile memory device in which electrical isolation characteristics are improved.
2. Description of the Related Art
A non-volatile memory device, which is a type of a semiconductor device, continuously stores memorized content even when supply of power is stopped. Generally, a memory cell of a non-volatile memory device includes a gate electrode comprised of a floating gate and a control gate and a drain or source region adjacent to the gate electrode.
An electrically erasable and programmable read only memory (EEPROM) device is included within the group of non-volatile memory devices, and a NAND type EEPROM device configured so that a plurality of transistors can be connected in series to one bit line is typical. Such a NAND-type EEPROM device is favorable for high integration.
A conventional method of manufacturing a non-volatile memory device will now be described by taking the NAND-type non-volatile memory device as an example.
FIG. 1
is a cross-sectional view of an isolation region after forming a control gate of a conventional non-volatile memory device.
To be more specific, an isolation layer
20
for defining an active region is formed on a semiconductor substrate
10
. A tunnel oxide
15
and a floating gate pattern is formed on the semiconductor substrate
10
. An interlayer insulating layer covering the floating gate pattern is formed, and a control gate layer is then formed. The control gate layer, the interlayer insulating layer, and the floating gate pattern are patterned by a self alignment method to form a gate structure. Impurities, e.g., phosphorous (P), are implanted into the active region of the semiconductor substrate
10
exposed adjacent to the floating gate, to thus form a drain or source region
30
.
The isolation layer
20
adjacent to the gate structure in this process may be damaged by the self alignment method.
To be more specific, the unpatterned interlayer insulating layer covers one sidewall of the floating gate pattern, and the control gate layer extends over and covers the isolation layer
20
. Accordingly, over etch to a depth as much as the thickness of the floating gate pattern or more must be performed in the self alignment patterning process to expose the side wall of the floating gate pattern by removing the part of the interlayer insulating layer covering the sidewall of the floating gate pattern. This is because the part of the interlayer insulating layer covering the sidewall of the floating gate pattern has a thickness in the vertical direction that is equal to or greater than the thickness of the floating gate pattern.
However, only the interlayer insulating layer and the control gate layer cover a part of the isolation layer
20
adjacent to the floating gate pattern. Hence, the isolation layer
20
can be etched out to about the height of the floating gate layer or higher by this excessive etching.
This undesired etching of the isolation layer
20
becomes excessive with the high integration of a non-volatile memory device, and hence, may cause several problems. To be more specific, the high integration of the non-volatile memory device requires a reduction in the size of a cell, and thus, further a reduction in the size of the isolation layer
20
which is formed between active regions. The reduction in the size of the isolation layer
20
requires a reduction in the size of a bird's beak, etc. to secure the width of an active region. To do this, the isolation layer
20
should become remarkably thinner.
Furthermore, the high integration of the non-volatile memory device requires a reduction in design rule. Thus, the floating gate, etc. overlaps the edge of the isolation layer
20
by only a very short length. The relatively thin edge of the isolation layer
20
, e.g., a bird's beak portion, can be exposed by the floating gate, etc. The isolation layer
20
remaining after over-etched becomes significantly thinner.
The reduction in the thickness of the isolation layer
20
due to the above-described self alignment patterning process prevents a process margin from being obtained in the subsequent process. For example, in an ion implantation process where the isolation layer
20
is used as an implanting mask, when the isolation layer
20
becomes thinner as described above, in particular, when its edge becomes thinner, the thickness of the isolation layer
20
may not be maintained to or over the distance which ions penetrate. Hence, impurities implanted in the ion implantation process can penetrate below the isolation layer
20
.
Such a penetration of impurities below the isolation layer
20
can cause channeling of impurities below the isolation layer
20
. Such a channeling phenomenon can have a degrading effect on the operation characteristics of the non-volatile memory device by lowering the concentration of a channel stop layer formed below the isolation layer
20
.
Also, the reduction in the thickness of the edge of the isolation layer
20
can generate an effect of reducing the electrical isolation distance between the drain or source regions
30
as shown by A in FIG.
1
. That is, the drain or source region
30
is extended to thus probably degrade the characteristics of isolation.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a method of manufacturing a non-volatile memory device, by which an isolation layer can be prevented from becoming thinner, and the electrical characteristics of the isolation layer can be prevented from being degraded in an ion implantation process due to a reduction in the thickness of the isolation layer.
According to an aspect of the present invention to achieve the above object, an isolation layer is formed on a semiconductor substrate including a cell array part and a peripheral circuit part. A floating gate pattern is formed exposing the semiconductor substrate in the peripheral circuit part with a tunnel oxide layer interposed between the floating gate pattern and the semiconductor substrate in the cell array part, and an interlayer insulating layer covering the floating gate pattern is formed. A control gate layer is formed, which covers the interlayer insulating layer and the semiconductor substrate in the peripheral circuit part while interposing a gate oxide layer between the control gate layer and the semiconductor substrate. A mask layer is further formed on the control gate layer, after forming the control gate layer. The mask layer is used as an ion-implantation mask in a subsequent first or third ion-implantation step.
The isolation layer in the peripheral circuit part is protected by leaving a part of the control gate layer covering the peripheral circuit part, and a control gate, an interlayer insulating layer pattern, and a floating gate in the cell array part are formed by sequentially patterning the control gate layer, the interlayer insulating layer, and the floating gate pattern in the cell array part. A first low-concentration impurity layer is formed by first ion-implantation of impurities into the semiconductor substrate adjacent to the floating gate using the control gate and the control gate layer covering the peripheral circuit part as an ion-implantation mask. Preferably, the mask layer covering the control gate layer is used as an ion implantation mask. Arsenic is used as the first impurity, and the arsenic is ion-implanted at an energy of about 30 KeV to 60 KeV in the first ion-implantation step. It is preferable that the arsenic is ion-implanted at an energy of about 30 KeV to 45 KeV in the first ion-implantation step.
A gate is formed in the peripheral circuit part by patterning the control gate layer in the peripheral circuit part with a photo resist pattern shielding the cell array part. Here, the cell array part is covered by the photoresist pattern such that impurity can be prevented from being injected upon ion imp

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