Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-11
2003-04-22
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000, C438S597000, C438S618000, C438S621000, C438S626000
Reexamination Certificate
active
06551877
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing semiconductor devices. More particularly, the present invention relates to a method of manufacturing memory devices.
2. Description of Related Art
Memory is an important semiconductor device for holding data or programs. As computer microprocessors becomes more powerful and programming software increases in size and complexity, demands for memory storage area also increase proportionately. To produce large capacity memory units at a cheaper cost, all semiconductor manufacturers are striving to increase the level of integration of devices.
For example, dynamic random access memory (DRAM) is a common type of memory device because DRAM has a high level of integration, a good read/write capability and a relatively low production cost.
Basic structure of a memory cell inside the DRAM includes a metal-oxide-semiconductor (MOS) device and a capacitor. One source/drain region of a MOS device is electrically connected to a bit line while the other source/drain region of the MOS device is electrically connected to a capacitor. Data is stored as charges in the capacitor of the DRAM cell. However, as the level of integration increases, dimensions of each memory cell and area occupation of the associated capacitor must be reduced. To maintain a relatively constant capacitance value, the capacitor usually has a capacitor over bit line (COB) design. This design has a bigger cross-sectional area at the bottom of the capacitor so that overall surface area of the capacitor is increased.
In DRAM, the fabrication of dielectric layer, the formation of contacts and the laying of metallic interconnecting wires after the formation of MOS device over a substrate are all important manufacturing steps. For DRAM having a COB design, two or more layers of conductive layers are used to match up with the increased connections necessary to link up increased number of devices after miniaturization. Although a multiple conductive layer design is able to resolve interconnection problems caused by an increase in level of integration, an increase in device thickness leads to the contact opening having a larger aspect ratio. Ultimately, the alignment and etching window for fabricating the contact openings is correspondingly reduced. To minimize alignment and etching problems, a self-aligned contact (SAC) process is now commonly used to form the necessary connections between the substrate and the metallic wires.
A conventional self-aligned contact process includes forming a plurality of gate structures over a substrate and sequentially forming a silicon nitride liner layer and an inter-layer dielectric layer over the substrate. Thereafter, a portion of the inter-layer dielectric layer is removed to form a plurality of openings above the source/drain regions. The exposed liner layer is removed to form bit line contact openings and storage node contact openings. Conductive material is deposited into the bit line contact openings and the storage node contact openings to form bit line contacts (or landing pads) and storage node contacts (or storage node landing pads).
However, as the level of integration for semiconductor devices continues to increase, the conventional DRAM contact manufacturing process has the following problems. Since the bit line contact openings and the storage node openings are separate from each other and have different opening dimensions (size of the bit line contact opening is greater than the storage node contact opening), etching rate between the bit line contact openings and the storage node contact openings are different (etching rate of the bit line contact openings is higher than the storage node contact openings). Hence, in the process of etching the inter-layer dielectric layer to form the contact openings, the substrate of larger contact openings is exposed much sooner than the smaller contact openings. In other words, the contact openings having a smaller dimension are still covered by a residual inter-layer dielectric layer when all of the inter-dielectric layer covering the larger contact openings have been removed. To ensure that the interior of each contact opening is free of any inter-layer dielectric material, the etching period is extended. However, an extension of the etching time may lead to an over-etching of substrate, gate cap and spacers inside larger size contact openings. Ultimately, the damaged substrate or the subsequently formed bit line contacts or the storage node contacts may form a short circuit with the gate.
Furthermore, dimensions of contact opening also reduce due to a tightening of design rules. Consequently, the problem of overlapping openings is increasingly severe leading to greater difficulties in performing the self-aligned contact etching process.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of manufacturing a memory device capable of increasing performance stability and reducing production cost.
A second object of this invention is to provide a method of manufacturing a memory device capable of forming precise self-aligned contact openings without damaging surrounding gate cap layer or spacers and preventing the gate electrode from forming a short circuit with a subsequently formed contact.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a memory device. A substrate having a plurality of active regions, a plurality of gate structures and a plurality of source/drain regions thereon is provided. An inter-layer dielectric layer is formed over the substrate. A global opening is formed inside the inter-layer dielectric layer. The global opening at least exposes the active regions for forming a plurality of contacts above the source/drain regions and the gate structures between them. A conductive layer filling the global opening is formed over the substrate. A portion of the conductive layer and the inter-layer dielectric layer is removed until the upper surface of the gate cap layer is exposed to form the plurality of contacts that connect with the source/drain regions electrically.
In this invention, a global opening is formed inside the inter-layer dielectric layer. The global opening exposes the source/drain regions for forming contacts and the associated gate structures between the source/drain regions inside the active region. Thereafter, conductive material is deposited into the global opening and any excess conductive material above the gate structure, the inter-layer dielectric layer and the liner layer is removed until the upper surface of the gate cap layer is exposed. Ultimately, a plurality of disconnected contacts is formed. Since there is no need to form openings that separately expose the source region and the drain region in the inter-layer dielectric layer, performance stability and processing window for the semiconductor devices is improved and production cost is lowered. Furthermore, precise and reliable self-aligned contact openings are formed without any damages to the gate cap layer or the spacers. Consequently, short circuit between the gate and subsequently formed bit line contact or storage node contact is prevented.
In addition, a liner layer may form over the substrate before the inter-layer dielectric layer. This liner layer is made from a material having an etching rate that differs from the inter-layer dielectric layer. Hence, the liner layer may serve as an etching stop layer when the inter-layer dielectric layer is etched to from the global opening. The liner layer may further serve as a protective layer protecting the substrate or the gate structure against any damages due to etching. The exposed liner layer inside the global opening may be removed subsequently.
This invention also provides an alternative method of forming a dynamic random access memory. A substrate having an active region thereon is provided. The active region furth
Chen Jack
Jiano Chyun Intellectual Property Office
Jr. Carl Whitehead
Powerchip Semiconductor Corp.
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