Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-08-27
2001-12-04
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S315000
Reexamination Certificate
active
06326266
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior European Patent Application No. 97-830427.7, filed Aug. 27, 1997, the entire disclosure of which is herein incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices having matrices of virtual ground cells, and more specifically to processes for manufacturing semiconductor virtual ground memory devices that have a matrix of floating gate memory cells and continuous bit lines extending across the substrate as discrete parallel stripes.
BACKGROUND OF THE INVENTION
Conventional semiconductor electronic memory devices of the EPROM or FLASH EPROM type are constructed in the form of cell matrices divided into sections that are essentially sub-matrices formed of memory cell blocks having predetermined dimensions. Each block has bias and address lines to select the individual memory cells and decode the information contained therein. Such a semiconductor memory device is described in Applicant's European Patent No. 0 573 728.
In particular, this patent discloses a process for making an integrated device of the EPROM or FLASH-EPROM type in which the individual memory blocks include a cell matrix made up of a plurality of mutually orthogonal word lines and bit lines. The cross points of the word lines and bit lines define the memory cells. This type of structure is known in the art as a “tablecloth” or cross point matrix, and is peculiar in that the bit lines are formed on the semiconductor substrate by parallel, continuous diffused stripes. The metal contacts are only formed at the opposite ends of the bit lines and provide termination pads for each of the memory blocks. Thus, there are few metal contacts in the area of the integrated memory cells, so the capacity for integration on semiconductor substrate is greatly expanded.
A circuit diagram of this basic configuration is shown in FIG.
1
. As shown, opposite contact regions
4
border the floating gate memory cells
3
. Each memory cell
3
is bounded by a corresponding continuous main bit line
7
, and a discontinuous bit line or bit line “segment”
17
. Each segment is connected to an adjacent continuous bit line through an address active clement
20
, and there are right and left address active elements
20
for each bit line segment.
Additionally, FLASH memory cells require field oxide isolation areas in order to maintain a high capacitive ratio between the control gate and the floating gate. However, the field oxide occupies much of the circuit area of the semiconductor substrate. Considering the particular instances of EPROMs (which are erased by UV radiation) and OTP memories (which cannot be erased), a high capacitive ratio between the control gate and the floating gate appears to be overkill and adds to the overall dimensions of the integrated circuit. Thus, there is a need for an organizational structure for the memory cells that retains the matrix configuration yet enables the circuit area occupied by the matrix to be greatly reduced.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide semiconductor memory devices having virtual ground cell matrices in which very high density memory circuits are produced with reduced dimensions. The field oxide isolation areas are removed from the matrix region for the memory cells of the memory device, and the bit lines in the matrix are isolated by having regions doped opposite from the bit lines.
It is another object of the present invention to provide a process for manufacturing such semiconductor memory devices. N-wells are formed in at least one of the substrate portions to accommodate P-channel transistors, the active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the mask. This produces a semiconductor device in which the area occupied by memory cells in a matrix configuration is greatly reduced.
A first embodiment of the present invention provides a semiconductor memory device having a matrix of memory cells formed on a matrix portion of a substrate. A plurality of continuous bit lines extend across the matrix portion of the substrate as discrete parallel stripes separated by active areas, and at least some transistors for memory cell selection are formed outside the matrix portion of the substrate. Further, the matrix portion of the substrate does not contain any isolation field oxide regions.
A second embodiment of the present invention provides a method for manufacturing a semiconductor memory device having a matrix of floating gate memory cells formed with a plurality of continuous bit lines that extend across the matrix as discrete parallel stripes. According to the method, N-wells are formed in at least a first portion of a substrate in order to accommodate P-channel transistors, active areas for transistors are defined by using a screening mask and growing an isolation layer through apertures in the screening mask, and the memory cell matrix is formed in a second portion of the substrate. Further, the screening mask used for defining the active areas does not have apertures over the second portion of the substrate.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.
REFERENCES:
patent: 4719184 (1988-01-01), Cantarelli et al.
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 5081056 (1992-01-01), Mazzali et al.
patent: 5313419 (1994-05-01), Chang
patent: 5712178 (1998-01-01), Cho et al.
patent: 5717635 (1998-02-01), Akatsu
European Search Report Dec. 18, 1997.
Bergemont et al., “Low Voltage NVG: A new High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications”, Sept. 1996, IEEE Transactions olectron Devices, vol. 43, No. 9, pp. 1510-1517.
Brambilla Claudio
Caprara Paolo
Cassio Valerio
Creda Manlio Sergio
Bongini Stephen
Chaudhuri Olik
Fleit Kain Gibbons Gutman & Bongini P.L.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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