Method of manufacturing a semiconductor power device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257S330000, C257SE29133

Reexamination Certificate

active

07842574

ABSTRACT:
A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.

REFERENCES:
patent: 6194741 (2001-02-01), Kinzer et al.
patent: 6291298 (2001-09-01), Williams et al.
patent: 6528355 (2003-03-01), Hirler et al.
patent: 6800509 (2004-10-01), Lin et al.
patent: 2003/0030092 (2003-02-01), Darwish et al.
patent: 2004/0041207 (2004-03-01), Takano et al.

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