Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-06
2007-02-06
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S288000
Reexamination Certificate
active
10987340
ABSTRACT:
A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.
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Choi Yong-suk
Kim Jae-Hwang
Kim Seong-gyun
Yoon Seung-beom
Goodwin David
Huynh Andy
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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