Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-13
2004-02-17
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000
Reexamination Certificate
active
06693008
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device, more particularly, to a technology suitable for applications in a method of manufacturing a semiconductor integrated circuit device having a trench isolation portion and a semiconductor integrated circuit device having a trench isolation portion.
BACKGROUND OF THE INVENTION
Instead of element isolation technologies based on the local oxidization of silicon (LOCOS) method, a trench filled type element isolation technology has been adopted with an increase in capacity of elements. According to the technology, after an isolation trench is formed on a semiconductor substrate by etching, an insulating film is deposited on a main surface of the semiconductor substarate by a CVD method. By filling the isolation trench, an element isolation portion is formed. As the insulating film (or isolation film) for filling the isolation trench, for example, mixture gas of tetraethoxysilane (TEOS) and ozone (O
3
) may be used. Alternatively, the insulating film may be formed by causing decomposition reaction between monosilane and oxygen through high-density plasma.
The technology is described in Japanese Patent Laid-Open No. 235157/1993, which discloses a technology for filling an insulating film into field regions with different widths.
SUMMARY OF THE INVENTION
The inventor hereof has realized in the technology for filling the isolation trench a problem below:
With an increase in fineness of the insulation trench, the isolation trench can not be fully filled with the isolation film, leaving un-filled portions as holes. When flattening the isolation trench after the filling process, the holes left in the isolation trench are exposed to a surface of the isolation trench. Due to an electrode material left in the holes during electrode formation thereafter, failures such as a short between electrode wires are caused. As a result, reliability and yield of a semiconductor integrated circuit device are deteriorated.
It is an object of the present invention to provide a technology allowing to fill an insulating film into an isolation trench fully without forming holes on a top of the insulating film filled within the isolation trench.
Also, it is another object of the present invention to provide a technology allowing to fill an insulating film into a trench formed between adjacent patterns fully without forming holes on a top of the insulating film filled within the trench.
These and other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings.
Typical effects obtained by the present invention disclosed herein may be described simply as follows:
The present invention includes the step of filling an isolation trench formed on a semiconductor substrate by filling it up to predetermined middle depth with an insulating film formed by a coating method and then stacking an insulating film thereon.
The present invention includes the step of filling an isolation trench formed on a semiconductor substrate by filling it up to predetermined middle depth with an insulating film formed by a coating method and then stacking an insulating film formed by a chemical vapor deposition method thereon.
The present invention includes the step of filling a trench formed between adjacent patterns formed on a semiconductor substrate by filling it up to predetermined middle depth with an insulating film formed by a coating method and sequentially stacking an insulating film formed by a chemical vapor deposition method thereon.
The present invention includes the steps of forming dummy patterns in one isolation region with a relatively large planer area of isolation regions with relatively different planar areas on a semiconductor substrate and filling an isolation trench formed on each of isolation regions with relatively different planar areas on a semiconductor substrate by filling it up to predetermined middle depth with an insulating film formed by a coating method and sequentially stacking an insulating film formed by a chemical vapor deposition method thereon.
The present invention includes the steps of forming a plurality of patterns, which are adjacent to each other, on a semiconductor substrate; filling a trench formed between the plurality of patterns, which are adjacent to each other, up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method; and filling a remaining depth portion of the trench into which the first insulating film is filled with a second insulating film.
In the manufacturing method, the plurality of patterns include a MISFET gate electrode and a dummy gate electrode, or an element isolation trench and a dummy pattern.
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IBM Technical DIsclosure Bulletin, Publication Date—Apr. 1, 1985, vol. 27, Issue 11, p. No. 6524.
Hotta Katsuhiko
Ichizoe Hiroyuki
Maruyama Hiroyuki
Saikawa Takeshi
Sato Hidenori
Antonelli Terry Stout & Kraus LLP
Jr. Carl Whitehead
Renesas Technology Corporation
Vesperman William C
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