Method of manufacturing a semiconductor device having a gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S299000, C438S303000, C438S585000

Reexamination Certificate

active

07008835

ABSTRACT:
In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

REFERENCES:
patent: 4908332 (1990-03-01), Wu
patent: 6770552 (2004-08-01), Wieczorek et al.
patent: 2001-189451 (2001-07-01), None
patent: 93-701217 (1993-06-01), None
patent: 01-23858 (2001-03-01), None
patent: 03-56932 (2003-07-01), None
patent: 92/00792 (1992-01-01), None
patent: 99/12853 (1999-03-01), None

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