Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-16
2006-05-16
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S156000, C438S157000, C438S176000, C438S231000, C438S596000
Reexamination Certificate
active
07045429
ABSTRACT:
In a method of manufacturing a semiconductor device, a device including gate electrodes and asymmetric source and drain regions is formed by employing a semiconductor layer structure. The short channel effect is prevented in the resulting device even though the gate electrodes are of a dimension on the order of nanometers. Additionally, the gate electrodes and asymmetric source and drain regions of the semiconductor device may be precisely formed to have dimensions on the nanometer scale because a semiconductor layer structure is used in the process for manufacturing the semiconductor device.
REFERENCES:
patent: 6180502 (2001-01-01), Liang
patent: 9-252121 (1997-09-01), None
patent: 10-0221627 (1999-06-01), None
Ghani, T., et al., “Asymmetric Source/Drain Extension Transistor Structure for High Performance Sub-50nm Gate Length CMOS Devices,” 2001 Symposium on VLSI Technology Digest of Technical Papers, 2001.
Kang Hee-Sung
Liu Jin-Hua
Ryou Choong-Ryul
Flynn Nathan J.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Tran Tan
LandOfFree
Method of manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3625446