Method of manufacturing a MOS integrated circuit having componen

Details Method of manufacturing a MOS integrated circuit having componen Method of manufacturing a MOS integrated circuit having componen

1996-05-10

2000-09-05

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438201, 438264, 438287, 438275, H01L 21336

Patent

active

061142034

ABSTRACT:
The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms of resistance to degradation due to the passage of charges through it during the operation of the memory, the method provides for a step for the high-temperature nitriding of the oxide. According to a variant, the nitrided oxide formed on the areas intended for the components of the peripheral circuits is removed and then formed again by a similar thermal oxidation treatment followed by high-temperature nitriding.

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Ma, Zhi-Jian et al., "Optimization of Gate Oxide N.sub.2 O Anneal for CMOSFET's at Room and Cryogenic Temperatures", IEEE, vol. 4, No. 8: 1364-1371, Aug. 1994.

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