Method of manufacturing a memory device having improved...

Details Method of manufacturing a memory device having improved... Method of manufacturing a memory device having improved...

2008-07-22

2008-07-22

Lebentritt, Michael S. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S200000, C438S201000, C438S258000, C438S264000, C438S265000, C438S287000, C438S296000, C257SE21210

Reexamination Certificate

active

07402492

ABSTRACT:
In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.

REFERENCES:
patent: 6642573 (2003-11-01), Halliyal et al.
patent: 2003/0047755 (2003-03-01), Lee et al.
patent: 2003/0211692 (2003-11-01), Lee
patent: 2006/0160303 (2006-07-01), Ang et al.
patent: 10-2003-0086825 (2003-11-01), None
patent: 10-2004-0046341 (2004-06-01), None

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