Method of manufacturing a capacitor in a memory device

Details Method of manufacturing a capacitor in a memory device Method of manufacturing a capacitor in a memory device

1999-12-20

2001-08-28

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S241000, C438S242000, C438S250000, C438S251000, C438S252000, C438S253000, C438S254000, C438S255000, C438S256000, C438S393000, C438S394000, C438S395000, C438S396000, C438S397000, C438S398000, C438S399000

Reexamination Certificate

active

06281066

ABSTRACT:

FIELD OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a method of manufacturing a capacitor of a high-integrated memory device using a tantalum oxide film (Ta
2
O
5
) as a dielectric.
2. Description of the Prior Art
Currently, the semiconductor memory device can be mainly classified into a read/write memory and a read only memory (ROM). In particularly, the read/write memory may be classified into a dynamic RAM (hereinafter called DRAM) and a static RAM. The DRAM is currently the highest integrated device, which is consisted of one unit cell composed of one transistor and one capacitor.
Meanwhile, as the integration degree of the memory device is advanced, the capacity of the memory has increased four times in three years. Currently, many studies have been focused on 256 Mb(mega bit) DRAM and 1 Gb (giga bit). However, as the integration degree of the DRAM becomes higher, the cell area functioning to read and write the electrical signal must be reduced to 0.5 &mgr;m
2
in case of 256 Mb. Also, the area of the capacitor that is one of the basic elements of the cell, must be reduced to 0.3 &mgr;m
2
. Due to this reason, in case of a higher integrated device more than 256 Mb class, the technology used in the conventional semiconductor process has its limitation. In other words, if the capacitor is manufactured by using SiO
2
/Si
3
N
4
etc. of the conventional dielectric materials in manufacturing a 64 Mb DRAM even though the thickness of the thin film becomes thinner, the area in which the capacitor occupies must exceed 6 times the cell area in order to secure the necessary capacitance. Due to this reason as the capacitor can not be used as a flat shape, the sectional area has to be extended in other ways. Thus, various technologies to increase the sectional area, that is, to increase the surface area of the storage node of the capacitor such as a stack capacitor structure or a trench type capacitor structure or a semi-spherical type poly-silicon film, have been proposed so far.
However in case of the device more than 256 Mb class using SiO
2
/Si
3
N
4
group dielectric materials, the thickness of the device could not be further reduced in order to increase the capacitance. Also, if the structure of the device becomes complicated in order to increase the sectional area of the capacitor, it makes the manufacturing process complicated, thus increasing the manufacturing cost and lowering the throughput. Thus, it is extremely difficult that the conventional method is applied the DRAM more than 256 Mb class, by which a three dimensional cubic structure is formed to increase its sectional area for satisfying the storage static capacitance.
In order to solve these problems, a study has been made on Ta
2
O
5
dielectric thin film so as to replace the SiO
2
/Si
3
N
4
group dielectric. However, the capacitance of the Ta
2
O
5
dielectric thin film is at most 2-3 times compared to that of the SiO
2
/Si
3
N
4
group dielectric. Thus, in order that the Ta
2
O
5
dielectric thin film can be applied to the DRAM more than 256 Mb class, its dielectric thin film has to be reduced at its minimum. In this case, there is a problem that the leak current is increased. That is, in case of the Ta
2
O
5
thin film, it is said that the leak current characteristic of the Ta
2
O
5
capacitor is good at its amorphous state, but the Ta
2
O
5
thin film can not be used itself since its effective oxide film (Tox) is thick in thickness. Therefore, though a method of crystallizing the Ta
2
O
5
thin film at high temperature may be used so as to reduce the effective oxide film (Tox), there is a problem that the value of the leak current of the Ta
2
O
5
capacitor is increased.
Meanwhile, the technology for manufacturing the capacitor using Ta
2
O
5
is advantageous in securing a given static capacitance due to its high dielectric constant. However, it must use only TiN as an upper electrode material or a TiN/poly-silicon double structure, in order to prohibit the interface reactance of Ta
2
O
5
with an upper electrode and a lower electrode and to prevent deterioration of its capacitance characteristic. Further, the lower electrode must use poly-silicon to the surface of which RTN (rapid thermal nitration) is processed.
However the conventional Ta
2
O
5
capacitor constructed above may cause deterioration in the electrical characteristic such as an increase of the effective oxide film (Tox), an increase of the leak current etc. upon a high thermal process. Also, it may cause a problem of the step coverage due to a higher integration of the device. Thus, a lot of studies have been made on solving these problems.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problems involved in the prior art, and to provide a method of manufacturing a capacitor of a semiconductor memory device, which can improve the step coverage of the electrode while preventing deterioration of the electrical characteristic due to a subsequent thermal process.
In order to accomplish the above object, the method of manufacturing a method of manufacturing a capacitor of a memory device according to the present invention comprises a method of manufacturing a capacitor of a memory device comprises forming a lower electrode; forming a tantalum oxide film of a dielectric thin film on lower electrode; forming a CVD TiN layer on the tantalum oxide film; forming a MOCVD TiN layer on the CVD TiN layer: and forming a poly-silicon layer on the MOCVD TiN layer whereby an upper electrode in which said CVD TiN layer, said MOCVD TiN layer and said poly-silicon layer arc stacked is formed.
In the present method, the step of forming the lower electrode includes forming a poly-silicon layer on a substrate, forming a MOCVD TiN layer on the poly-silicon layer and the a CVD TiN layer on the MOCVD TiN.


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