Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-03
2009-12-08
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000, C438S739000, C438S740000, C438S508000
Reexamination Certificate
active
07629218
ABSTRACT:
Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same. In a method of manufacturing a capacitor having improved characteristics, an insulation layer, including a pad therein, may be formed on a substrate. An etch stop layer may be formed on the insulation layer. A mold layer may be formed on the etch stop layer. The mold layer may be partially etched by a first etching process to form a first contact hole exposing the etch stop layer. The mold layer may be partially etched by a second etching process to form a second contact hole. The exposed etch stop layer may be etched by a third etching process to form a third contact hole exposing the pad. A native oxide layer on the exposed pad may be removed by a fourth etching process to form a capacitor contact hole. A conductive layer may be formed in the capacitor contact hole to form a capacitor.
REFERENCES:
patent: 5436187 (1995-07-01), Tanigawa
patent: 6271084 (2001-08-01), Tu et al.
patent: 6337267 (2002-01-01), Yang
patent: 6528368 (2003-03-01), Park
patent: 6583056 (2003-06-01), Yu et al.
patent: 6700153 (2004-03-01), Oh et al.
patent: 6773998 (2004-08-01), Fisher et al.
patent: 6780777 (2004-08-01), Yun et al.
patent: 2004/0159909 (2004-08-01), Kim et al.
patent: 2004-186379 (2004-07-01), None
patent: 2005-41682 (2005-05-01), None
patent: 2005-64208 (2005-06-01), None
Wolf et al., “Dry Etching for VLSI Fabrication,” Silicon Processing for the VLSI Era: vol. 1—Process Technology, Lattice Press (1986), pp. 547-551.
Kang Man-Sug
Kim Tae-Han
Lee Keum-Joo
Lee Woo-Sung
Harness & Dickey & Pierce P.L.C.
Samsung Electronics Co,. Ltd.
Thomas Toniae M
Wilczewski M.
LandOfFree
Method of manufacturing a capacitor and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a capacitor and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a capacitor and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4056119