Method of manufacture of self-aligned JFET

Details Method of manufacture of self-aligned JFET Method of manufacture of self-aligned JFET

1996-08-26

1997-12-30

Graybill, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

438192, H01L 21337

Patent

active

057029873

ABSTRACT:
A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.

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Ghandhi, "VLSI Fabrication Principles Silicon and Gallium Arsenide", pp. 19-21, John Wiley & Sons, 1994 Month Unknown.

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