Method of manufacture of self-aligned floating gate, flash memor

Details Method of manufacture of self-aligned floating gate, flash memor Method of manufacture of self-aligned floating gate, flash memor

1997-09-26

2000-01-11

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438296, H01L 218247

Patent

active

060135514

ABSTRACT:
A method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate includes the following steps. Form a blanket silicon oxide layer over the substrate. Form a blanket floating gate conductor layer over the silicon oxide layer. Pattern the blanket silicon oxide layer, the floating gate conductor layer and the substrate in a patterning process with a single floating gate electrode mask forming floating gate electrodes from the floating gate conductor layer and the silicon oxide layer; and simultaneously form trenches in the substrate adjacent to the floating gate electrode and aligned with the floating gate electrodes thereby patterning the active region in the substrate. Form a blanket dielectric layer on the device filling the trenches and planarized with the top surface of the floating gate electrodes. Form an interconductor dielectric layer over the device including the floating gate electrodes. Form a control gate conductor over the interconductor dielectric layer.

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Aritome et al. "A 0.67.mu.m.sup.2 Self-Aligned Shallow Trench. Isolation Cell (SA-ST1 Cell) for 3V-only 256 Mbit NAND EEPROMS" IEDM 9461. pp. 3.6.1-3.6.4.

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