Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Patent
1999-09-10
2000-09-26
Bowers, Charles
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
438761, 438786, 438787, 438788, H01L 2348, H01L 2952
Patent
active
061242160
ABSTRACT:
A method of forming a low-k dielectric insulating layer includes forming the dielectric insulating layer and then removing hydrogen bonds in the dielectric insulating layer. The dielectric layer as formed is preferably a HSQ film which contains the structure Si--O--H. Hydrogen is removed from the dielectric layer by either: a heat treatment in plasma, an ozone reduction process, an ion implantation process, or electron beam bombardment.
REFERENCES:
patent: 4756977 (1988-07-01), Haluska et al.
patent: 5320868 (1994-06-01), balance et al.
patent: 5703404 (1997-12-01), Matsuura
patent: 5719084 (1998-02-01), Mallon et al.
patent: 5776834 (1998-07-01), Avanzino et al.
patent: 5818111 (1998-10-01), Jeng et al.
patent: 5837618 (1998-11-01), Avanzino et al.
M. Matsuura et all, "A Highly Reliable Self-planarizing Low-k Intermetal Dielectric for Sub-quarter Micron Interconnects," 1997 IEEE, IEDM 97-785 through 97-788.
N. Oda et al., "O.6 um Pitch Highly Reliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG for Sub-Quarter Micron CMOS Technology," 1997 Symposium on VLSI Technology Digest of Technical papers, pp. 79-80.
B. Zhao et al, "A Cu/Low-k Dual Damascene Interconnect for High Performance and Low Cost integrated Circuits," 1998 Symposium on VLSI Technology Digest ofTechnical Papers, pp. 28-29.
R. S. List et al., "Integration of Ultra-Low-k Xerogel Gapfill Dielectric for High Performance Sub-0.18um Interconnects," 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 77-78.
K. Yoshiyama et al., "A Simple Sub-0.3um CMOS Technology with Five-Level Interconnect using Al-plug and HSQ of Low-k for High Performance Processor," 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 55-56.
Kim Chung-Howan
Kim Dong-yun
Kim Tae-Ryong
Ko Ho
Song Jong-Heui
Bowers Charles
Kilday Lisa
Samsung Electronics Co,. Ltd.
LandOfFree
Method of making intermetal dielectric layers having a low diele does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making intermetal dielectric layers having a low diele, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making intermetal dielectric layers having a low diele will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2099853